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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 113/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
113
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Concentration Highway Interface
(continued)
Rate adaptation is required for all DS1 formats between the 1.544 Mbits/s line rate and 2.048 Mbits/s,
4.966 Mbits/s, or 8.182 Mbits/s CHI rate. This is achieved by means of stuffing eight idle time slots into the existing
twenty-four time slots of the T1 frame. Idle time slots can occur every fourth time slot (starting in the first, second,
third, or fourth time slot) or be grouped together at the end of the CHI frame as described in register FRM_PR43
bit 0—bit 2. The positioning of the idle time slots is the same for transmit and receive directions. Idle time slots con-
tain the programmable code of register FRM_PR23. Unused time slots can be disabled by forcing the TCHIDATA
interface to a high-impedance state for the interval of the disabled time slots.
CHI Parameters
The CHI parameters that define the receive and transmit paths are given in Table 57.
Table 57. Summary of the T7630’s Concentration Highway Interface Parameters
Name
HWYEN
Description
Highway Enable (FRM_PR45 bit 7).
A 1 in this bit enables the transmit and receive
concentration highway interfaces. This allows the framer to be fully configured before
transmission to the highway. A 0 forces the idle code as defined in register
FRM_PR22, to be transmitted to the line in all payload time slots while TCHIDATA is
forced to a high-impedance state for all CHI transmitted time slots.
Concentration Highway Master Mode (PRM_PR45 bit 4).
The default mode
CHIMM = 0 enables an external system frame synchronization signal (TCHIFS) to
drive the transmit CHI. A 1 enables the transmit CHI to generate a system frame syn-
chronization signal from the receive line clock. The transmit CHI system frame syn-
chronization signal is generated on the TCHIFS output pin. Applications using the
receive line clock as the reference clock signal of the system are recommended to
enable this mode and use the TCHIFS signal generated by the framer. The receive
CHI path is
not
affected by this mode.
CHI Double Time-Slot Mode (FRM_PR65 bit 1 and FRM_PR66 bit 1).
CHIDTS
defines the 4.096 Mbits/s and 8.192 Mbits/s CHI modes. CHIDTS = 0 enables the 32
contiguous time-slot mode. This is the default mode. CHIDTS = 1 enables the double
time-slot mode in which the transmit CHI drives TCHIDATA for one time slot and then
3-states for the subsequent time slot, and the receive CHI latches data from RCHI-
DATA for one time slot and then ignores the following time slot and so on. CHIDTS = 1
allows two CHIs to interleave frames on a common bus.
Transmit Frame Edge (FRM_PR46 bit 3).
TFE = 0 (or 1), TCHIFS is sampled on the
falling (or rising) edge of TCHICK. In CHIMM (CHI master mode), the TCHIFS pin
outputs a transmit frame strobe to provide synchronization for TCHIDATA. When
TFE = 1 (or 0), TCHIFS is centered around rising (or falling) edge of TCHICK. In this
mode, TCHIFS can be used for receive data on RCHIDATA. The timing for TCHIFS in
CHIMM = 1 mode is identical to the timing for TCHIFS in CHIMM = 0 mode.
Receive Frame Edge (FRM_PR46 bit 7).
RFE = 0 (or 1), RCHIFS is sampled on the
falling (or rising) edge of RCHICK.
CHI Data Rate (FRM_PR45 bit 2 and bit 3).
Two-bit control for selecting the CHI
data rate. The default state (00) enables the 2.048 Mbits/s.
CDRS Bit:2 3CHI Data Rate
0 0 2.048 Mbits/s
0 1 4.096 Mbits/s
1 0 8.192 Mbits/s
1 1 Reserved
CHIMM
CHIDTS
TFE
RFE
CDRS0—CDRS1
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| T8110 | Version History |
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