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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁數(shù)： | 71/210頁 |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
71
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats
(continued)
CEPT Loss of Time Slot 16 Multiframe Align-
ment (LTS16MFA)
Loss of basic frame alignment forces the receive framer
into a loss of time slot 16 signaling multiframe align-
ment state. In addition, as defined in ITU Rec. G.732
Section 5.2, time slot 16 signaling multiframe is
assumed lost when two consecutive time slot 16 multi-
frame 4-bit all-zero patterns is received with an error.
Also, the time slot 16 multiframe is assumed lost when,
for a period of two multiframes, all bits in time slot 16
are in state 0. This state is reported by way of the sta-
tus registers FRM_SR1 bit 1. Once basic frame align-
ment is achieved, the receive framer will initiate a
search for the time slot 16 multiframe alignment. During
a loss of time slot 16 multiframe alignment state:
I
The updating of the signaling data is halted.
I
The received control bits forced to the binary 1 state.
I
The received remote multiframe alarm indication sta-
tus bit is forced to the binary 0 state.
I
Optionally, the transmit framer can transmit to the
line the time slot 16 signaling remote multiframe
alarm if register FRM_PR41 bit 4 is set to 1.
I
Optionally, the transmit framer can transmit the alarm
indication signal (AIS) in the system transmit time
slot 16 data if register FRM_PR44 bit 6 is set to 1.
CEPT Loss of Time Slot 16 Multiframe Align-
ment Recovery Algorithm
The time slot 16 multiframe alignment recovery algo-
rithm is as described in ITU Rec. G.732 Section 5.2.
assumed frame alignment has been achieved, time slot
16 multiframe alignment is deemed to have occurred
when the 4-bit time slot 16 multiframe pattern of 0000
is found in time slot 16 for the first time, and the preced-
ing time slot 16 contained at least one bit in the binary
1 state.
CEPT Time Slot 0 FAS/NOT FAS Control
Bits
FAS/NOT FAS Si- and E-Bit Source
The Si bit can be used as an 8 kbits/s data link to and
from the remote end, or in the CRC-4 mode, it can be
used to provide added protection against false frame
alignment. The sources for the Si bits that are transmit-
ted to the line are the following:
I
CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the
TSiF control bit (FRM_PR28 bit 1) is transmitted in
bit 1 of all FAS frames and the TSiNF control bit
(FRM_PR28 bit 2) is transmitted in bit 1 of all NOT
FAS frames.
I
The CHI system interface (CEPT with no CRC-4 and
FRM_PR28 bit 0 = 0)
*
.
This option requires the received system data (RCHI-
DATA) to maintain a biframe alignment pattern where
frames containing Si bit information for the NOT FAS
frames have bit 2 of time slot 0 in the binary 1 state fol-
lowed by frames containing Si bit information for the
FAS frames that have bit 2 of time slot 0 in the binary 0
state. This ensures the proper alignment of the Si
received system data to the transmit line Si data.
Whenever this requirement is not met by the system,
the transmit framer will enter a loss of biframe align-
ment condition (indication is given in the status regis-
ters) and then search for the pattern; in the loss of
biframe alignment state, transmitted line data is cor-
rupted (only when the system interface is sourcing Sa
or Si data). When the transmit framer locates a new
biframe alignment pattern, an indication is given in the
status registers and the transmit framer resumes nor-
mal operations.
I
CEPT with CRC-4
: manual transmission of
E bit = 0:
— If FRM_PR28 bit 0 = 0, then the TSiF bit
(FRM_PR28 bit 1) is transmitted in bit 1 of frame
13 (E bit) and the TSiNF bit (FRM_PR28 bit 2) is
transmitted in bit 1 of frame 15 (E bit).
— If FRM_PR28 bit 0 = 1, then each time 0 is written
into TSiF (FRM_PR28 bit 1) one E bit = 0 is trans-
mitted in frame 13, and each time 0 is written into
TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmit-
ted in frame 15.
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system
transparently, FRM_PR29 must first be momentarily written to
001xxxxx (binary). Otherwise, the transmit framer will not be able
to locate the biframe alignment.
The receive E-bit processor will halt the monitoring of received E
bits during loss of CRC-4 multiframe alignment.
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