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| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 93/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
93
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Alarms and Performance Monitoring
(continued)
Receive Line Pattern Monitor—Using Register
FRM_SR7
The receive framer pattern monitor continuously moni-
tors the received line, detects the following fixed framed
patterns, and indicates detection in register FRM_SR7
bit 6 and bit 7.
I
The pseudorandom test pattern as described by ITU
Rec. O.151 and illustrated in Figure 43. Detection of
the pattern is indicated by register FRM_SR7 bit
6 = 1.
I
The quasi-random test pattern described in AT&T
Technical Reference 62411[5] Appendix and illus-
trated in Figure 42. Detection of the pattern is indi-
cated by register FRM_SR7 bit 7 = 1.
In DS1 mode, the received 193 bit frame must consist
of 192 bits of pattern plus 1 bit of framing information.
In CEPT mode, the received 256 bit frame must consist
of 248 bits of pattern plus 8 bits (TS0) of framing infor-
mation. No signaling, robbed bit in the case of T1 and
TS16 signaling in the case of CEPT, may be present for
successful detection of these two test patterns.
To establish lock to the pattern, 256 sequential bits
must be received without error. When lock to the pat-
tern is achieved, the appropriate bit of register
FRM_SR7 is set to a 1. Once pattern lock is estab-
lished, the monitor can withstand up to 32 single bit
errors per frame without a loss of lock. Lock will be lost
if more than 32 errors occur within a single frame.
When such a condition occurs, the appropriate bit of
register FRM_SR7 is deasserted. The monitor then
resumes scanning for pattern candidates.
Receive Line Pattern Detector—Using Register
FRM_PR70
Framed or unframed patterns indicated in Table 47 may
be detected using register FRM_PR70. Detection of
the selected test pattern is indicated when register
FRM_SR7 bit 4 is set to 1. Selection of a framed or
unframed test pattern is made through FRM_PR70 bit
3. Bit errors in the received test pattern are indicated
when register FRM_SR7 bit 5 = 1. The bit errors are
counted and reported in registers FRM_SR8 and
FRM_SR9, which are normally the BPV counter regis-
ters. (In this test mode, the BPV counter registers do
not count BPVs but count only bit errors in the received
test pattern.)
Table 47. Register FRM_PR70 Test Patterns
Pattern
Register FRM_PR70
Bit 7
0
0
0
0
0
Bit 6
0
0
0
0
1
Bit 5
0
0
1
1
0
Bit 4
0
1
0
1
0
MARK (all ones AIS)
QRSS (2
20
– 1 with zero suppression)
2
5
– 1
63 (2
6
– 1)
511 (2
9
– 1)
511 (2
9
– 1) reversed
2047 (2
11
– 1)
2047 (2
11
– 1) reversed
2
15
– 1
2
20
– 1
2
20
– 1
2
23
– 1
1:1 (alternating)
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
0
0
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