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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
13
28
LLOOP
O
Local Loop-back Output Pin (to the XRT7300 DS3/E3/STS-1 LIU IC).
This output pin is intended to be connected to the LLOOP input pin of the XRT7300
LIU IC. The user can command this signal to toggle “high” and, in turn, force the LIU
into the “Local Loop-back” mode. (For a detailed description of the XRT7300 LIU IC’s
operation during Local Loop-back, please see the XRT7300 DS3/E3/STS-1 LIU IC
Data Sheet).
Writing a “1” to bit 1 of the “Line Interface Drive Register” (Address = 72h) will cause
this output pin to toggle “high”. Writing a “0” to this bit-field will cause the RLOOP out-
put to toggle “l(fā)ow”.
Note:
If the user is not using the XRT7300 DS3/E3/STS-1 LIU IC, then he/she can
use this output pin for a variety of other purposes.
29
IntB*
O
Interrupt Request Output:
This open-drain, active-low output signal will be asserted
when the UNI device is requesting interrupt service from the local microprocessor. This
output pin should typically be connected to the “Interrupt Request” input of the local
microprocessor.
30
RxLCD
O
Loss of Cell Delineation Indicator:
This active-high output pin will be asserted
whenever the Receive Cell Processor has experienced a “Loss of Cell Delineation”.
This pin will return “l(fā)ow” once the Receive Cell Processor has regained Cell Delinea-
tion.
31
GND
***
Ground Pin Signal
32
CSB*
I
Chip Select Input:
This active-low input signal selects the Microprocessor Interface
Section of the UNI device and enables Read/Write operations between the “l(fā)ocal”
microprocessor and the UNI on-chip registers and RAM locations.
33
RDB_DS
I
Read Data Strobe (Intel Mode):
If the microprocessor interface is operating in the
Intel Mode, then this input will function as the RD* (READ STROBE) input signal from
the local
μ
P
. Once this active low signal is asserted, then the UNI will place the con-
tents of the addressed registers (within the UNI) on the Microprocessor Data Bus
(D[15:0]). When this signal is negated, the Data Bus will be tri-stated.
Data Strobe (Motorola Mode):
If the microprocessor interface is operating in the
Motorola mode, then this pin will function as the active low Data Strobe signal.
34
RxGFC
O
Receive GFC Nibble Field Serial Output pin:
This pin, along with the RxGFCClk
and the RxGFCMSB pins form the “Receive GFC Nibble-Field” serial output port. This
pin will serially output the contents of the GFC Nibble field of each cell that is pro-
cessed through the Receive Cell Processor. This data is serially clocked out of this pin
on the rising edge of the RxGFCClk signal. The Most Significant Bit (MSB) of each
GFC value is designated by a pulse at the RxGFCMSB output pin.
35
WRB_RW
I
Write Data Strobe (Intel Mode):
If the microprocessor interface is operating in the
Intel Mode, then this active low input pin functions as the WR* (Write Strobe) input sig-
nal from the
μ
P Once this active-low signal is asserted, then the UNI will latch the
contents of the
μ
P Data Bus, into the addressed register (or RAM location) within the
UNI IC.
R/W Input Pin (Motorola Mode):
When the Microprocessor Interface Section is oper-
ating in the “Motorola Mode”, then this pin is functionally equivalent to the “R/W*” pin.
In the Motorola Mode, a “READ” operation occurs if this pin is at a logic “1”. Similarly,
a WRITE operation occurs if this pin is at a logic “0”.
PIN DESCRIPTION (CONT’D)
P
IN
N
O
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S
YMBOL
T
YPE
D
ESCRIPTION