XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
90
3.3.2.58
PMON Transmitted Valid Cell Count—MSB
This “Reset-upon-Read” register, along with the
“PMON Transmitted Valid Cell Count—LSB” register
(Address = 3Bh) contains a 16-bit representation of
the number of “User (or Assigned) Cells” that have
been generated and transmitted by the Transmit Cell
Processor, since the last read of these registers. This
register contains the MSB (or Upper byte) value of
this 16 bit expression.
3.3.2.59
PMON Transmitted Valid Cell Count—LSB
This “Reset-upon-Read” register, along with the
“PMON Transmitted Valid Cell Count—MSB” register
(Address = 3Ah) contains a 16-bit representation of
the number of “User (or Assigned) Cells” that have
been generated and transmitted by the Transmit Cell
Processor, since the last read of these registers. This
register contains the LSB (or Lower byte) value of
this 16 bit expression.
3.3.2.60
PMON Holding Register
This register is of use if the user is operating the UNI
in the 8-bit
μ
P Access Mode. When the
μ
P reads out a
particular PMON Counter, One Second Accumulator,
or Test Cell Error Accumulator (16 bit registers), it will
read out one of two 8-bit registers. The contents of
the other 8-bit register will be stored in this register.
For more information on this operation, please see
Section 3.5.
3.3.2.61
One Second Error Status Register
Address = 3Ah, PMON Transmitted Valid Cell Count—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Tx Valid Cell Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 3Bh, PMON Transmitted Valid Cell Count—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Tx Valid Cell Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 3Ch, PMON Holding Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
PMON Hold Value
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Address = 3Dh, One Second Error Status Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Errored Sec
Severe Errored Sec
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0