á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
273
Note:
1. The selection of this bit also affects the width of the
Transmit UTOPIA Data bus.
2. The UTOPIA Data Bus width will be 8 bits, upon
power up or reset. Therefore, the user must write a
“1” to this bit in order to set the width of the
Receive UTOPIA (and the Transmit UTOPIA data
bus) to 16 bits.
7.4.2.1.3
Selecting the Cell Size (Number of
Octets per Cell)
The UNI allows the user to select the number of oc-
tets per cell that the Receive UTOPIA Interface block
will process. Specifically, the user has the following
cell size options.
If the UTOPIA Data Bus is 8 bits wide then the user
can choose:
– 52 bytes (with no HEC byte in the cell), or
– 53 bytes (with either a dummy or actual HEC
byte in the cell)
If the UTOPIA Data Bus is 16 bits wide then the
user can choose:
– 52 bytes (with no HEC byte in the cell), or
– 54 bytes (with either a dummy or actual HEC
byte, and a stuff byte in the cell)
The user makes his/her selection by writing the appro-
priate data to bit 3 (CellOf52Bytes) within the UTOPIA
Configuration Register, as depicted below.
The following table specifies the relationship between
the value of this bit and the number of octets/cell that
the Receive UTOPIA Interface block will process.
Note:
This selection applies to both the Transmit UTOPIA
and Receive UTOPIA interface blocks. Additionally, the
shaded selection reflects the default condition upon power
up or reset.
An Advisory to Users
The user must insure that the ATM Layer processor
only reads in (from the Receive UTOPIA Interface
block) the “configured” number of octets per cell,
following the latest assertion of the RxSoC output
pin. If the ATM Layer processor continues to try to
read-in more octets, it will end up reading in in-valid
data.
T
ABLE
60: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
WITHIN
B
IT
0 (U
T
W
IDTH
16)
WITHIN
THE
UTOPIA
C
ONFIGURATION
R
EGISTER
,
AND
THE
OPERATING
WIDTH
OF
THE
UTOPIA D
ATA
B
US
V
ALUE
FOR
U
T
W
IDTH
16
W
IDTH
OF
UTOPIA D
ATA
B
US
0
8 bit wide Data Bus
1
16 bit wide Data Bus
UTOPIA Configuration Register: (Address = 6Ah)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Handshake Mode
M-PHY
CellOf52 Bytes
TFIFODepth[1, 0]
UtWidth16
RO
R/W
R/W
R/W
R/W
R/W
T
ABLE
61: T
HE
R
ELATIONSHIP
BETWEEN
THE
VALUE
OF
B
IT
3 (C
ELL
O
F
52B
YTES
)
WITHIN
THE
UTOPIA
C
ONFIGURATION
R
EGISTER
,
AND
THE
NUMBER
OF
OCTETS
PER
CELL
THAT
WILL
BE
PROCESSED
BY THE
T
RANSMIT
AND
R
ECEIVE
UTOPIA I
NTERFACE
BLOCKS
.
C
ELL
O
F
52 B
YTES
N
UMBER
OF
B
YTES
/C
ELLS
0
53 bytes when the UTOPIA Data Bus width is 8 bits wide.
54 bytes when the UTOPIA Data Bus width is 16 bits wide.
1
52 bytes, regardless of the width of the UTOPIA Data Bus