XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
88
3.3.2.51
PMON Received Idle Cell Count—LSB
This “Reset-upon-Read” register, along with the “PMON
Received Idle Cell Count—MSB” register (Address =
32h) contains a 16 bit representation of the number of
“Idle Cells” that have been detected by the Receive Cell
Processor, since the last read of these register. This
register contains the LSB (or Lower Byte) value of this
16-bit expression.
3.3.2.52
PMON Received Valid Cell Count—MSB
This “Reset-upon-Read” register, along with the “PMON
Received Valid Cell Count—LSB” register (Address =
35h) contains a 16 bit representation of the number
of “User (or Assigned) Cells” that have been detected
by the Receive Cell Processor, since the last read of
this register. This register contains the MSB (or Up-
per Byte) value of this 16-bit expression.
3.3.2.53
PMON Received Valid Cell Count—LSB
This “Reset-upon-Read” register, along with the “PMON
Received Valid Cell Count—MSB” register (Address =
34h) contains a 16 bit representation of the number
of “User (or Assigned) Cells” that have been detected
by the Receive Cell Processor, since the last read of
this register. This register contains the LSB (or Lower
Byte) value of this 16-bit expression.
3.3.2.54
PMON Discarded Cell Count—MSB
Address = 33h, PMON Received Idle Cell Count—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Rx Idle Cell Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 34h, PMON Received Valid Cell Count—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Rx Valid Cell Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 35h, PMON Received Valid Cell Count—LSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Rx Valid Cell Count—Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Address = 36h, PMON Discarded Cell Count—MSB
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Cell Drop Count—High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0