XRT7245
DS3 UNI FOR ATM
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PRELIMINARY
REV. 1.03
IV
Address = 12h, RxDS3 FEAC Register .........................................................................................................73
Address = 13h, RxDS3 FEAC Interrupt Enable/Status Register ................................................................73
Bit 4—FEAC Valid ..........................................................................................................................................73
Bit 3—RxFEAC Remove Interrupt Enable ....................................................................................................74
Bit 2—RxFEAC Remove Interrupt Status .....................................................................................................74
Bit 1—RxFEAC Valid Interrupt Enable .........................................................................................................74
Bit 0—RxFEAC Valid Interrupt Status ..........................................................................................................74
Address = 14h, RxDS3 LAPD Control Register ...........................................................................................74
Bits 7–3 Enable5 F(4)–F(0) ............................................................................................................................74
Bit 2 RxLAPD Enable .....................................................................................................................................74
Bit 1 RxLAPD (Message Frame Reception Complete) Interrupt Enable ...................................................74
Bit 0 RxLAPD (Message Reception Complete) Interrupt Status ................................................................74
Address = 15h, Rx DS3 LAPD Status Register ............................................................................................75
Bit 6—RxAbort (Receive Abort Sequence) ..................................................................................................75
Bits, 5 and 4—RxLAPDType[1, 0] .................................................................................................................75
Bit 3—RxCR (Command/Response) Type ...................................................................................................75
Bit 2—Rx FCS (Frame Check Sequence) Error ...........................................................................................75
Bit 1—End Of Message ..................................................................................................................................75
Bit 0—Flag Present ........................................................................................................................................75
Address = 16h, Tx DS3 Configuration Register ..........................................................................................76
Bit 7—Tx Yellow Alarm ..................................................................................................................................76
Bit 6—Tx X-Bit (Force X bits to “1”) .............................................................................................................76
Bit 5—Tx Idle (Pattern) ..................................................................................................................................76
Bit 4—Tx AIS (Pattern) ...................................................................................................................................76
Bit 3—Tx LOS (Loss of Signal) .....................................................................................................................76
Bit 2—FERF on LOS ......................................................................................................................................77
Bit 1—FERF on OOF ......................................................................................................................................77
Bit 0—FERF on AIS ........................................................................................................................................77
Address = 17h, Tx DS3 M-Bit Mask Register ...............................................................................................77
Bit 7-5: TxFEBEDat[2:0] .................................................................................................................................77
Bit 4—FEBE Register Enable ........................................................................................................................77
Bit 3—Transmit Erred P-Bit ...........................................................................................................................77
Bit 2–0 M-Bit Mask[2:0] ..................................................................................................................................78
Address = 18h, Tx DS3 F-Bit Mask1 Register ..............................................................................................78
Bits 3–0 F-Bit Mask[27:24] ............................................................................................................................78
Address = 19h, Tx DS3 F-Bit Mask2 Register ..............................................................................................78
Bits 7–0 F-Bit Mask[23:16] ............................................................................................................................78
Address = 1Ah, Tx DS3 F-Bit Mask3 Register .............................................................................................79
Bits 7–0 F-Bit Mask[15:8] ..............................................................................................................................79
Address = 1Bh, Tx DS3 F-Bit Mask4 Register .............................................................................................79
Bits 7–0 F-Bit Mask[7:0] ................................................................................................................................79
Address = 1Ch, Tx DS3 FEAC Configuration and Status Register ...........................................................79
Bit 4—TxFEAC Interrupt Enable ...................................................................................................................79
Bit 3—TxFEAC Interrupt Status ....................................................................................................................80