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參數(shù)資料
| 型號(hào)： | XRT7245 |
| 廠(chǎng)商： | Exar Corporation |
| 英文描述： | DS3 ATM User Network Interface(DS3異步傳輸模式用戶(hù)網(wǎng)絡(luò)接口) |
| 中文描述： | DS3自動(dòng)柜員機(jī)用戶(hù)網(wǎng)絡(luò)接口（DS3異步傳輸模式用戶(hù)網(wǎng)絡(luò)接口） |
| 文件頁(yè)數(shù)： | 65/324頁(yè) |
| 文件大?。?/td> | 4103K |
| 代理商： | XRT7245 |
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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
65
Bit 6—Rx PLCP Interrupt Status
This “Read Only” bit field indicates whether or not a
“Receive PLCP Processor block” interrupt request is
pending.
If this bit-field is “0”, then no “Receive PLCP Proces-
sor block” interrupt request is pending.
However, if this bit-field is “1” then a “Receive PLCP
Processor block” interrupt request is pending and await-
ing service. Since the Receive PLCP Processor block
has two different “potential” interrupt sources, the us-
er should include a read to the Rx PLCP Interrupt
Status Register (Address = 46h), during in the Inter-
rupt Service Routine, in order to determine the exact
cause of the interrupt.
This bit-field will be cleared (set to “0”) after the local
μP has read the “Rx PLCP Interrupt Status” register.
Bit 5—Rx CP (Cell Processor) Interrupt Status
This “Read Only” bit field indicates whether or not a
“Receive Cell Processor block” interrupt request is
pending.
If this bit-field is “0”, then no “Receive Cell Processor
block” interrupt request is pending.
However, if this bit-field is “1” then a “Receive Cell
Processor block” interrupt request is pending and
awaiting service. Since the Receive Cell Processor
has several “potential” interrupt sources, the user
should include a read to the “Rx CP Interrupt Status”
Register (Address = 4Fh), during the Interrupt Ser-
vice Routine, in order to determine the exact cause of
the interrupt.
This bit-field will be cleared (set to “0”) after the local
μP has read the “Rx CP Interrupt Status” register.
Bit 4—Rx UTOPIA Interrupt Status
This “Read Only” bit field indicates whether or not a
“Receive UTOPIA Interface block” interrupt request is
pending.
If this bit-field is “0”, then no “Receive UTOPIA Interface
block” interrupt request is pending.
However, if this bit-field is “1”, then a “Receive UTOPIA
Interface block” interrupt request is pending and
awaiting service. Since the Receive UTOPIA has
multiple potential interrupt sources, the user should
include a read to the “Rx UT Interrupt Enable/Status
Register” (Address = 6Bh), in order to determine the
exact cause of the interrupt.
This bit-field will be cleared (set to “0”) after the local
μP has read the “Rx UT Interrupt Enable/Status” reg-
ister.
Bit 3—Tx UTOPIA Interrupt Status
This “Read Only” bit field indicates whether or not a
“Transmit UTOPIA Interface block” interrupt request
is pending.
If this bit-field is “0”, then no “Transmit UTOPIA Inter-
face block” interrupt request is pending.
However, if this bit-field is “1”, then a “Transmit UTOPIA
Interface block” interrupt request is pending and await-
ing service. Since the Transmit UTOPIA has multiple
potential interrupt sources, the user should include a
read to the “Tx UTOPIA Interrupt/Status Register”
(Address = 6Eh) in the Interrupt Service Routine, in
order to determine the exact cause of the interrupt.
This bit-field will be cleared (set to “0”) after the local
μP has read the “Tx UTOPIA Interrupt/Status” register.
Bit 2—Tx CP (Cell Processor) Interrupt Status
This “Read Only” bit-field indicates whether or not a
“Transmit Cell Processor block” interrupt request is
pending.
If this bit-field is “0”, then no “Transmit Cell Processor
block” interrupt request is pending.
However, if this bit-field is “1”, then a “Transmit Cell
Processor block” interrupt request is pending and
awaiting service. Since the Transmit Cell Processor
has only one potential interrupt source (Data Path In-
tegrity Error Occurrence), the user should still include
a read to the “Tx CP Control” Register (Address = 60h),
in the Interrupt Service Routine, in order to reset this
interrupt assertion.
This bit-field will be cleared (set to “0”) after the local
μP has read the “Tx CP Control” Register.
Bit 1—Tx DS3 (Framer) Interrupt Status
This “Read Only” bit-field indicates whether or not a
“Transmit DS3 Framer block” interrupt request is
pending.
If this bit-field is “0”, then a “Transmit DS3 Framer
block” interrupt request is pending.
However, if this bit-field is “1”, then a “Transmit DS3
Framer” block interrupt request is pending and await-
ing service. Since the Transmit DS3 Framer has two
potential interrupts (FEAC Message Transfer Complete,
and LAPD Message Transfer Complete), the user
should include reads to the following two registers,
during the Interrupt Service Routine, in order to
determine the exact cause of the interrupt.
Tx DS3 FEAC Configuration and Status Register
(Address = 1Ch)
Tx DS3 LAPD Status/Interrupt Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT7288IP | CEPT1 Line Interface |
| XRT7288 | CEPT1 Line Interface(CEPT1線(xiàn)接口) |
| XRT7288IW | CEPT1 Line Interface |
| XRT7295AE | E3 (34.368Mbps) Integrated line Receiver |
| XRT7295AE_03 | E3 (34.368Mbps) Integrated line Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7250 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7250ES-PCI | 功能描述:界面開(kāi)發(fā)工具 Evaluation Board for XRT7250 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
| XRT7250IQ100 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7288 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:CEPT1 Line Interface |
| XR-T7288 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:CEPT1 Line Interface |
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