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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
XV
Rx PLCP Interrupt Status Register (Address = 46h) ................................................................................ 247
Bit 0—“PLOF Interrupt Status .................................................................................................................... 248
Bit 1—POOF Interrupt Status ..................................................................................................................... 248
Receive Cell Processor ..................................................................................................248
The HUNT State ........................................................................................................................................... 252
The PRE-SYNC State ................................................................................................................................... 252
The SYNC State ........................................................................................................................................... 252
Rx CP Interrupt Status Register (Address = 4Eh) .................................................................................... 252
The SYNC State ........................................................................................................................................... 252
RxCP Configuration Register (Address = 4Ch) ........................................................................................ 253
The Overall Cell Filtering/Processing Approach within the Receive Cell Processor block ................. 253
RxCP Configuration Register (Address = 4Ch) ........................................................................................ 254
The “HEC Byte Error Correction/Detection” Algorithm ........................................................................... 254
The “Correction” State ................................................................................................................................ 254
RxCP Configuration Register (Address = 4Ch) ........................................................................................ 254
Monitoring of Single-Bit Errors, during HEC Byte Verification. .............................................................. 255
PMON Received Single HEC Error Count—MSB (Address = 2Eh) ......................................................... 255
PMON Received Single HEC Error Count—LSB (Address = 2Fh) .......................................................... 255
Monitoring of Multi-Bit Errors, during HEC Byte Verification ................................................................. 255
PMON Received Multiple-Bit HEC Error—MSB (Address = 30h) ............................................................ 255
PMON Received Multiple-Bit HEC Error—LSB (Address = 31h) ............................................................. 255
The “Detection” State ................................................................................................................................. 256
RxCP Additional Configuration Register (Address = 4Dh) ...................................................................... 256
Bit 1—Correction (Mode) Enable ............................................................................................................... 256
Bits 2 and 3—Correction Threshold [1, 0] ................................................................................................. 256
Filtering of Cells with HEC Byte Errors ..................................................................................................... 256
RxCP Configuration Register (Address = 4Ch) ........................................................................................ 257
Example—Idle Cell Filtering ....................................................................................................................... 257
Content of Header Byte-1 (of Incoming Cell) ............................................................................................ 257
Content of “Rx CP Idle Cell Mask Header Byte-1 Register ...................................................................... 257
Content of “Rx CP Idle Cell Header Byte-1 Register ................................................................................ 257
Comments .................................................................................................................................................... 258
Results of Comparison ............................................................................................................................... 258
Rx CP Idle Cell Pattern Header Byte-1 Register (Address = 50h) ........................................................... 258
Rx CP Idle Cell Pattern Header Byte-2 Register (Address = 51h) ........................................................... 258
Rx CP Idle Cell Pattern Header Byte-3 Register (Address = 52h) ........................................................... 258
Rx CP Idle Cell Pattern Header Byte-4 Register (Address = 53h) ........................................................... 259
Rx CP Idle Cell Mask Header—Byte 1 (Address = 54h) ............................................................................ 259
Rx CP Idle Cell Mask Header—Byte 2 (Address = 55h) ............................................................................ 259
Rx CP Idle Cell Mask Header—Byte 3 (Address = 56h) ............................................................................ 259
Rx CP Idle Cell Mask Header—Byte 4 (Address = 57h) ............................................................................ 259
PMON Received Idle Cell Count—MSB (Address = 32h) ......................................................................... 260
PMON Received Idle Cell Count—LSB (Address = 33h) .......................................................................... 260