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PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
79
3.3.2.26
Tx DS3 F-Bit Mask 3 Register
Bits 7–0 F-Bit Mask[15:8]
These “Read/Write” bit-fields allow the user to insert
errors into the thirteenth through twentieth F-bits of a
DS3 M-frame, for test and diagnostic purposes. The
Transmit DS3 Framer automatically performs an XOR
operation on the actual contents of these F-bit fields
to these register bit-fields. Therefore, for every “1”
that exists in these bit-fields, this will result in a
change of state for the corresponding F-bit, prior to
being transmitted to the Far-End Receive DS3 Framer.
If the user wishes to operate the Transmit DS3 Framer
in the normal mode (e.g., when no errors are being
injected into these F-bit fields of the outbound DS3
frames), then he/she must ensure that all of these bit-
fields are “0s”.
3.3.2.27
Tx DS3 F-Bit Mask 4 Register
Bits 7–0 F-Bit Mask[7:0]
These “Read/Write” bit-fields allow the user to insert
errors into the last eight F-bits of a DS3 M-frame, for
test and diagnostic purposes. The Transmit DS3
Framer automatically performs an XOR operation on
the actual contents of these F-bit fields to these reg-
ister bit-fields. Therefore, for every “1” that exists in
these bit-fields, this will result in a change of state for
the corresponding F-bit, prior to being transmitted to
the Far-End Receive DS3 Framer.
If the user wishes to operate the Transmit DS3 Framer
in the normal mode (e.g., when no errors are being
injected into these F-bit fields of the outbound DS3
frames), then he/she must ensure that all of these bit-
fields are “0s”.
3.3.2.28
Tx DS3 FEAC Configuration and Status Register
Bit 4—TxFEAC Interrupt Enable
This “Read/Write” bit-field allows the user to enable
or disable the “FEAC Message Transmission Com-
plete” interrupt.
Writing a “0” to this bit-field disables this interrupt.
Writing a “1” to this bit-field enables this interrupt.
Address = 1Ah, Tx DS3 F-Bit Mask3 Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
F-Bit Mask
(15)
F-Bit Mask
(14)
F-Bit Mask
(13)
F-Bit Mask
(12)
F-Bit Mask
(11)
F-Bit Mask
(10)
F-Bit Mask
(9)
F-Bit Mask
(8)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Address = 1Bh, Tx DS3 F-Bit Mask4 Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
F-Bit Mask
(7)
F-Bit Mask
(6)
F-Bit Mask
(5)
F-Bit Mask
(4)
F-Bit Mask
(3)
F-Bit Mask
(2)
F-Bit Mask
(1)
F-Bit Mask
(0)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Address = 1Ch, Tx DS3 FEAC Configuration and Status Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
TxFEAC Interrupt
Enable
TxFEAC Interrupt
Status
TxFEAC
Enable
TxFEAC
Go
TxFEAC
Busy
RO
RO
RO
R/W
RUR
R/W
R/W
RO
0
0
0
0
0
0
0
0