XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
94
Bit 1—POOF Interrupt Status
This “Read-Only” bit-field indicates whether the
“Change in POOF (Receive PLCP Processor Out of
Frame) condition” interrupt has been generated since
the last read of this register.
If this bit-field is “0”, then the “Change in POOF Condi-
tion” interrupt has not occurred since the last read of
this register. However, if this bit-field is “1”, then the
“Change in POOF Condition” interrupt has occurred
since the last read of this register.
Note:
This bit-field will be asserted under the following two
conditions:
The Receive PLCP Processor transitions from
the “In-Frame” or “Loss of Frame” condition to the
“Out of Frame” condition.
The Receive PLCP Processor transitions from
the “Out-of-Frame” condition to the “In-Frame”
condition.
1.
2.
The local
μ
P can read the “Rx PLCP Configuration/
Status” Register (Address = 44h), in order to determine
the current “POOF” status.
Bit 0—PLOF Interrupt Status
This “Read Only” bit-field indicates whether the
“Change in PLOF (Receive PLCP Processor Loss of
Frame) condition” interrupt has been generated since
the last read of this register.
If this bit-field is “0”, then the “Change in PLOF Con-
dition” interrupt has not occurred since the last read
of this register. However, if this bit-field is “1”, then the
“Change in PLOF Condition” interrupt has occurred
since the last read of this register.
Note:
This bit-field will be asserted under the following two
conditions:
The Receive PLCP Processor transitions from
the “In-Frame” condition to the “Loss of Frame”
condition.
The Receive PLCP Processor transitions from the
“Loss of Frame” or “Out of Frame” condition to the
“In-Frame” condition.
1.
2.
The local
μ
P can read the “Rx PLCP Configuration/
Status” Register (Address = 44h), in order to deter-
mine the current “PLOF” status.
3.3.2.71
Future Use
3.3.2.72
Tx PLCP A1 Byte Error Mask
This register allows the user to insert errors into the
A1 Byte of each outgoing PLCP Frame. The Transmit
PLCP Processor automatically performs the XOR
operation on the A1 byte of every outbound PLCP
frame with the contents of this register. Therefore, if
this register contains any “1s”, then errors will be
inserted into the A1 byte. If the user wishes to oper-
ate the Transmit PLCP in a normal mode (e.g., by
NOT inserting errors into the A1 byte), then he/she
must insure that this register contains the default
value, 00h.
Address = 47h, Future Use
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Address = 48h, Tx PLCP A1 Byte Error Mask
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
A1 Byte Error Mask
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0