XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
152
In Figure 34, the ATM Layer processor starts to write
in a new ATM cell, into the Transmit UTOPIA Interface
block, during clock edge #2. However, shortly after
the ATM Layer processor has written in word W22,
TxClav toggles “l(fā)ow”. In the “Cell-Level” Handshaking
mode, this means that the ATM Layer processor is
not permitted to write in the subsequent cell (e.g., the
cell which is to follow the one that is currently being
written into the Transmit UTOPIA Interface block).
Hence, the ATM Layer processor must complete writ-
ing in the current cell, and then halt with any further
write operations to the Transmit UTOPIA Interface
block. Therefore, the ATM Layer processor proceeds
to write in Words W23 through W26 and then
negates the TxEnB* signal after clock edge #28. At
this point, the ATM Layer processor must wait until
TxClav toggle “high” once again; before writing in the
next ATM cell.
6.1.2.3.1
Selecting the Operating Depth of the
Tx FIFO
The physical depth of the Tx FIFO is 16 cells. However,
for various reasons the user may wish to operate with
a smaller FIFO depth. Therefore, the UNI allows the
user to select an operating depth of 4, 8, 12 or the full
16 cells. The user can make this selection by writing
the appropriate data to Bits 1 and 2 (TFIFODepth[1, 0])
within the UTOPIA Configuration Register, as depict-
ed below .
The following table presents the values for both Bits 1
and 2 (within the UTOPIA Configuration Register)
and the corresponding operating depth of the
TxFIFO.
The operating depth of the Transmit FIFO will be 16
cells upon power up or reset. Therefore, the user
must write the appropriate data to these two bit-fields
in order to change this parameter.
6.1.2.3.2
Resetting the Tx FIFO via Software
Command
The UNI allows the user to reset the Tx FIFO, via
software command, without the need to implement a
master reset of the entire UNI device. This can be
accomplished by writing the appropriate data to bit 7
(TxFIFO Reset) of the Transmit UTOPIA Interrupt
Enable/Status Register as depicted below.
UTOPIA Configuration Register: Address = 6Ah
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Handshake Mode
M-PHY
CellOf52 Bytes
TFIFODepth[1, 0]
UtWidth16
RO
R/W
R/W
R/W
R/W
R/W
T
ABLE
14: T
HE
R
ELATIONSHIP
BETWEEN
T
X
FIFOD
EPTH
[1:0]
WITHIN
THE
UTOPIA C
ONFIGURATION
R
EGISTER
AND
THE
O
PERATING
D
EPTH
OF
THE
T
X
FIFO
B
IT
2
B
IT
1
O
PERATING
D
EPTH
OF
THE
T
RANSMIT
FIFO
0
0
16 cells
0
1
12 cells
1
0
8 cells
1
1
4 cells
Transmit UTOPIA—Interrupt/Status Register (Address—6Eh)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TFIFO Reset
Discard
Upon PErr
TPerr IntEn
TFIFO
ErrIntEn
TCOCA
IntEn
TPErr IntStat
TFIFO
OverInt Stat
TCOCA
IntStat
R/W
R/W
R/W
R/W
R/W
RUR
RUR
RUR