á
PRELIMINARY
DS3 UNI FOR ATM
XRT7245
REV. 1.03
93
Bit 3—Reframe (Receive PLCP Processor)
This “Read/Write” bit-field allows the user to command
the Receive PLCP Processor to perform a “Reframe”.
If the user invokes this command, the Receive PLCP
Processor will transition from the “In-Frame” state to
the “Loss-of-Frame” state. Afterwards, it will attempt
to re-acquire framing.
Writing a “1” to this bit-field will cause the Receive
PLCP Processor to Reframe.
For more information on PLCP Framing, please see
Section 7.2.2.1.4.
Bit 2—POOF (Receive PLCP OOF Condition) Status
This “Read-Only” bit-field indicates whether or not
the Receive PLCP Processor is in the “Out-of-Frame
(OOF)” condition or not. If this bit-field is “0”, then the
Receive PLCP Processor is either in the “In-Frame”
condition or in the “Loss-of-Frame” condition. If this
bit-field is “1”, then the Receive PLCP is currently in
the “OOF Condition”.
For more information on PLCP Framing, please see
Section 7.2.2.1.
Bit 1—PLOF (Receive PLCP LOF Condition) Status
This “Read-Only” bit-field indicates whether or not the
Receive PLCP Processor is in the “Loss of Frame
(LOF) condition or not. If this bit-field is “0”, then the
Receive PLCP Processor is either in the “In-Frame”
condition or in the “Out-of-Frame” condition. If this
bit-field is “1”, then the Receive PLCP Processor is
currently in the “LOF Condition”.
For more information on PLCP Framing, please see
Section 7.2.2.1.
Bit 0—Yellow Status
This “Read-Only” bit field indicates whether or not the
Receive PLCP Processor has detected a prolonged
“Yellow Alarm” indication in the G1 bytes of the in-
coming PLCP frames.
If a “Far-End” Receive PLCP Processor has trouble
receiving valid PLCP data from the “Near-End” Trans-
mit PLCP Processor, it (the Far End Transmit PLCP
Processor) will begin to transmit PLCP frames that
contain G1 bytes with the asserted “Yellow Alarm—
RAI” indicators. If the “Near-End” Receive PLCP Pro-
cessor determines that it has been receiving PLCP
frames with these kind of G1 bytes for a 2 to 10 second
period; then the Receive PLCP Processor will set this
bit-field to “1”.
For more information on the G1 Byte, within the
PLCP frame, please see Section 7.2.2.2.2.
3.3.2.69
Rx PLCP Interrupt Enable Register
Bit 1—POOF Interrupt Enable
This “Read-Write” bit-field allows the user to enable
or disable the “Change in POOF Condition” interrupt.
Writing a “0” to this bit-field disables this interrupt
condition. Writing a “1” to this bit-field enables this
interrupt condition.
Bit 0—PLOF Interrupt Enable
This “Read-Write” bit-field allows the user to enable
or disable the “Change in PLOF Condition” interrupt.
Writing a “0” to this bit-field disables this interrupt
condition. Writing a “1” to this bit-field enables this
interrupt condition.
3.3.2.70
Rx PLCP Interrupt Status Register
Address = 45h, Rx PLCP Interrupt Enable Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
POOF Interrupt Enable PLOF Interrupt Enable
RO
RO
RO
RO
RO
RO
R/W
R/W
0
0
0
0
0
0
0
0
Address = 46h, Rx PLCP Interrupt Status Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
POOF Interrupt Status
PLOF Interrupt Status
RO
RO
RO
RO
RO
RO
RUR
RUR
0
0
0
0
0
0
0
0