XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
200
This can be done by writing a “1” into Bit 0 of the UNI
Interrupt Enable Register, as depicted below.
3.
Write the new message into the “Transmit LAPD
Message” buffer immediately after the occur-
rence of the “One-Second” interrupt.
By timing the writes to the “Transmit LAPD Message”
buffer to occur immediately after the occurrence of
the “One-Second” interrupt, the user avoids conflict-
ing with the “one-second” transmissions of the LAPD
Message, and will transmit the correct messages to
the “Far-End” LAPD Receiver.
6.4.4.1.4
Manipulating the FEBE bit-fields of
the outbound DS3 Frames
The Transmit DS3 Framer allows the user to manipulate
the contents of the FEBE bit-fields in the outbound
DS3 frame. The user can accomplish this by writing
the appropriate data to the upper nibble of the Tx DS3
M-Bit Mask Register, as depicted below.
Each of these “FEBE-related” bit-fields are defined
below.
Bit 4—FEBE Register Enable
Writing a “1” to this “Read/Write” bit-field causes the
Transmit DS3 Framer to overwrite the internally
generated FEBE bits with the contents of the
TxFEBEDat[2:0] bit-fields (within this register) into
the outbound DS3 Frames.
Writing a “0” to this bit-field causes the Transmit DS3
Framer to transmit the internally generated FEBE bit-
values via the outbound DS3 Frames.
6.4.4.2
The Programmable Pattern Generator (PPG) allows
the user to override the Overhead Generator portion
of the Transmit DS3 Framer, in order to do the follow-
ing via software command:
Programmable Pattern Generator
Generate Yellow Alarms
Manipulate the X-bit (set them to “1”)
Generate the AIS Pattern
Generate the IDLE pattern
Generate the LOS pattern
Generate FERF (Yellow) Alarms, in response to
various conditions.
In some cases, the user may wish to generate these
signals in response to an interrupt, or upon sensing
certain conditions. In other cases, the user may wish
to generate some of these signals for Equipment
Testing Purposes.
The user can exercise each of these options by writ-
ing the appropriate data to the Tx DS3 Configuration
Address = 04h, UNI Interrupt Enable Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxDS3
Interrupt
Enable
RxPLCP
Interrupt
Enable
RxCP
Interrupt
Enable
Rx UTOPIA
Interrupt
Enable
Tx UTOPIA
Interrupt
Enable
Tx CP
Interrupt
Enable
Tx DS3
Interrupt
Enable
One Sec
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
Tx DS3 M-Bit Mask Register, Address = 17h
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
TxFEBE
Dat[2]
TxFEBE
Dat[1]
TxFEBE
Dat[0]
FEBE
Reg Enable
TxErr PBit
MBit Mask(2) MBit Mask(1) MBit Mask(0)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W