參數(shù)資料
型號： GT-64111
廠商： Galileo Technology Services, LLC
英文描述： System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器）
文件頁數(shù)： 101/130頁
文件大?。?/td> 881K
代理商： GT-64111
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
72
Revision 1.0
11.2.3 64-bit Devices
Notes:
1. System supports decrement.
2. System is litttle endian without decrement.
3. System is big endian without decrement.
4. dev_adr[21:0] is the output of the latch connected to AD[23:2], sampled by ALE.
5. Be careful if OEB is programmed at reset to have reverse polarity.
6. Regardless of endianess,
ECAS[0]* and OCAS[0]* always corresponds to SysAD[7:0] and AD[7:0].
ECAS[1]* and OCAS[1]* always corresponds to SysAD[15:8] and AD[15:8].
ECAS[2]* and OCAS[2]* always corresponds to SysAD[23:16] and AD[23:16].
ECAS[3]* and OCAS[3]* always corresponds to SysAD[31:24] and AD[31:24].
Co nnec t io n
Memory
Wi d t h
Co nnec t ..
.
To ...
Device Address1
64-bit
DAdr[2:0]
Even latch outputs
Odd latch outputs
LEAdrE
LEAdrO
{dev_adr[21:2], BAdrE[2:1]}4
{dev_adr[21:2}, BAdrO[2:1]}4
Even latch inputs
Odd latch inputs
Become burst address even (BAdrE[2:0])
Become burst address odd (BAdrO[2:0])
Even latch LE
Odd latch LE
Even bank address pins
Odd bank address pins
Device Address2
64-bit
DAdr[2:0]
Odd latch outputs
LEAdrO
{dev_adr[21:2], DAdr[2:1]}4
{dev_adr[21:2}, BAdrO[2:1]}4
Odd latch inputs
Become burst address odd (BAdrO[2:0])
Odd latch LE
Even bank address pins
Odd bank address pins
Device Address3
64-bit
DAdr[2:0]
Even latch outputs
LEAdrO
{dev_adr[21:2], BAdrE[2:1]}4
{dev_adr[21:2}, DAdr[2:1]}4
Even latch inputs
Become burst address even (BAdrE[2:0])
Even latch LE
Even bank address pins
Odd bank address pins
Device Data
(Latched)6
64-bit
AD[31:0]
Even latch I/Os B side
‘0’
LEE
OEE*
OEB5
AD[31:0]
Odd latch I/Os B side
‘0’
LEO
OEO*
OEB5
Even latch I/Os A side
Even bank data pins
Even latch CLKAB and CLKBA
Even latch LEAB and LEBA
Even latch OEBA*
Even latch OEAB
Odd latch I/Os A side
Odd bank data pins
Odd latch CLKAB and CLKBA
Odd latch LEAB and LEBA
Odd latch OEBA*
Odd latch OEAB
Device Control
64-bit
AD[31:0]
ALE
Control latch bit[0] output
Control latch bit[1] output
Control latch bit[23:2] outputs
Control latch bit[27:24] outputs
Control latch bit[31:28] outputs
Control latch inputs
Control latch LE
Becomes BootCS*
Becomes DevRW*
Becomes dev_adr [21:0]
Becomes DMAAck[3:0]*
Becomes CS[3:0]*
相關(guān)PDF資料
PDF描述
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器)
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