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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 59/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
34
Revision 1.0
longer access times requiring the GT-64111 to assert CAS* for two clocks instead of one.
5.1.4.2
RAS* to CAS*
The number of clocks between active RAS* and CAS* in write and read accesses can be programmed to be either two
(Figure 14) or three clocks (Figure 15). 3 clocks is the default delay between active RAS* and active CAS*.
Figure 14: Two Clock Delay between Active RAS* to Active CAS*
Figure 15: Three Clock Delay between Active RAS* to Active CAS*
Selecting the RAStoCASWr and RAStoCASRd parameter will depend on
DRAM RAS* to CAS* maximum delay time
TClk frequency
5.1.5
DRAM Bank Width and Location
Bit 6 of the DRAM Bank[3:0] Parameter registers (0x44c-0x458), BankWidth, specifies whether the data width of the
particular bank of DRAM is 32-bit (default) or 64-bit (32-bit interleaved). If the bank is set for 32-bit operation, it can
either reside on the even (default) or odd bank by setting bit 7, BankLoc. Selecting the even or the odd bank allows for
load balancing.
If the BankWidth is programmed to ‘1’ indicating the bank is set for 64-bit (32-bit interleaved), the setting of BankLoc is
irrelavent as both banks will be populated.
5.1.6
DRAM Performance
DRAM performance is based on the width of DRAM implemented (32 or 64-bit) as well as the setting of the DRAM
parameters. Table 16 lists the performance when the CPU reads a cache line (8 32-bit words) from DRAM. The perfor-
mance is measured from ValidOut* asserted by the processor with the Rd8Words command to the GT-64111 asserting
ValidIn* responding with the first datum. For example, 8-1-1-1-1-1-1-1 performances indicates 8 TClks from ValidOut*
asserted to ValidIn* asserted for the first datum and 1 TClk for every following datum (0 wait states). 10-3-3-3-3-3-3-3
indicates 10 TClks from ValidOut* asserted to ValidIn* asserted for the first datum and 3 TClks for every following
TClk
RAS*
. . .
CAS*
. . .
RAS* to CAS*,
2 TClks
TClk
RAS*
. . .
CAS*
. . .
RAS* to CAS*,
3 TClks
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