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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 60/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
datum (2 wait states).
TABLE 16. DRAM Performance
5.2
Device Controller
The device controller supports up to five banks of devices. Various access parameters can be programmed on a per
bank basis as each bank has its own parameters register (0x45c - 0x46c). The supported memory space of each
device bank can vary for each bank separately up to 32 Mbytes, and the width of each bank may be 8, 16, 32 or 64 bits
The maximum total device address space is 160Mbytes for five banks. The 5 individual chip selects are typically bro-
ken up into 4 individual device banks plus one chip select for a boot device (non-volatile memory).
BootCS* has the exact same functionality as CS[3:0] and devices which need to be read from and written to can be
attached to this chip select. The only difference between BootCS* and CS[3:0] is that by default, BootCS* is mapped to
the physical boot address of 0x1FC0.0000 (which can be reprogrammed) and its device width can be programmed by
input pins on reset.
Each device bank can have unique programmable timing parameters to accommodate different device types (e.g.
Flash, SRAM, ROM, I/O Controllers). The devices share the local AD bus with the DRAM, but unlike DRAM, the
devices use the AD bus as a multiplexed address and data bus.
In the address phase, the device controller puts on the AD bus an address with a corresponding Chip Select asserted.
ALE (and ADS* if programmed, Section 5.1.3) indicates the AD bus is outputing an address and CS*, DevRW* and
DMAAck*. ALE is used to latch the address, CS*, DevRW* and DMAAck* in an external 373. CS* should then be qual-
ified (OR-tied) with CSTiming*. A read or write cycle is indicated by the latched DevRW*. The CSTiming* signal will be
valid for the programmable number of cycles of the specific CS* that is active. TurnOff, AccToFirst and AccToNext can
be set in registers 0x45c - 0x46c for each bank’s read timing parameters (see Figure 16 for waveform example without
latches enabled, see Figure 17 for waveform example with latches enabled). ADStoWr, WrActive and WrHigh can be
set for each bank’s write timing parameters (see Figure 18 for waveform example). Please see Section 5.6 before con-
figuring these bits. AcctoFirst, AccToNext and WrActive can be extended by the Ready* pin (see Section 5.2.10).
5.2.1
TurnOff, bits [2:0]
TurnOff is the number of TClk cycles that the GT-64111 will not drive the memory bus after a read from a device. This
prevents contentions on the memory bus after a read cycle for a slow device. This parameter is measured from the the
number of cycles between the deassertion of DevOE* (an externally extracted signal which is the logical OR between
CSTiming* and inverted DevRW*) to an new AD bus cycle.
5.2.2
AccToFirst, bits [6:3]
AccToFirst defines the number of cycles in a read access from the assertion of CS* to the cycle that the data will be
latched (by external latches). This parameter can also be thought as the delay between the rising edge of TClk which
drives ALE HIGH to the the rising edge of TClk where the first data will be latched by the external latches. If there are
no latches in the system, AccToFirst defines the number of cycles between TClk which drives ALE HIGH to the rising
edge of TClk where the first data is latched into the GT-64111. This parameter can be extended by the Ready* pin.
5.2.3
AccToNext, bits [10:7]
AccToNext defined as the number of cycles in a read access from the cycle that the first data was latched to the cycle
1. 8-2-2-2-2-2-2-2 with 32-bit DRAMs and 8-1-1-1-1-1-1-1 clocks with 64-bit (32-bit interleaved) DRAMs is the performance for Ras-
toCasRd = 0 and CasRd = 0. In “wait-state” nomenclature this equates to 5-1-1-1-1-1-1-1 and 5-0-0-0-0-0-0-0.)
DRAM Width
RASt oC asR d = 0
CAS Rd = 0 1
RASt o C a s R d = 0
CASRd = 1
RASto Cas Rd = 1
CA SR d = 0
RASt o C a s R d = 1
C AS R d = 1
32-bit
8-2-2-2-2-2-2-2
9-3-3-3-3-3-3-3
9-2-2-2-2-2-2-2
10-3-3-3-3-3-3-3
64-bit (32-bit
interleaved)
8-1-1-1-1-1-1-1
9-1-2-1-2-1-2-1
9-1-1-1-1-1-1-1
10-1-2-1-2-1-2-1
相關(guān)PDF資料 |
PDF描述 |
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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