參數(shù)資料
型號： GT-64111
廠商： Galileo Technology Services, LLC
英文描述： System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器）
文件頁數(shù)： 14/130頁
文件大?。?/td> 881K
代理商： GT-64111
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
110
Revision 1.0
17.14 Interrupts
Interrupt Cause, Offset: 0xc18 (all bits are cleared by writing a value of ‘0’ by the CPU/ Local Master or PCI, unless stated otherwise)
Bits
Field Name
Function
Initial Value
0
IntSum
Interrupt summary. Logical OR of all the interrupt bits,
regardless of the Mask registers’ values.
0x0 Read only
1
MemOut
Asserts when the CPU/Local Master or PCI accesses
an address out of range in the Device Decoders or a
burst access to 8-/16-bit devices.
0x0
2
DMAOut
Asserts when the DMA accesses an address out of
range.
0x0
3
CPU/Local Master-
Out
Asserts when the CPU/Local Master accesses an
address out of the CPU/Local Master decode.
0x0
4
DMA0Comp
Asserts at completion of DMA Channel 0 transfer.
0x0
5
DMA1Comp
Asserts at completion of DMA Channel 1 transfer.
0x0
6
DMA2Comp
Asserts at completion of DMA Channel 2 transfer.
0x0
7
DMA3Comp
Asserts at completion of DMA Channel 3 transfer.
0x0
8
T0Exp
Asserts when Timer 0 expires.
0x0
9
T1Exp
Asserts when Timer 1 expires.
0x0
10
T2Exp
Asserts when Timer 2 expires.
0x0
11
T3Exp
Asserts when Timer 3 expires.
0x0
12
MasRdErr
Asserts when the GT-64111 detects a parity error dur-
ing a master read operation.
0x0
13
SlvWrErr
Asserts when the GT-64111 detects a parity error dur-
ing a slave write operation.
0x0
14
MasWrErr
Asserts when the GT-64111 detects a parity error dur-
ing a master write operation.
0x0
15
SlvRdErr
Asserts when the GT-64111 detects a parity error dur-
ing a slave read operation.
0x0
16
AddrErr
Asserts when the GT-64111 detects a parity error on
the address lines.
0x0
17
MemErr
Asserts when a memory parity error is detected.
Applicable only when an external parity checking
device is used.
0x0
18
MasAbort
Asserts upon master abort.
0x0
19
TarAbort
Asserts upon target abort.
0x0
20
RetryCtr
Asserts when the retry counter expires.
0x0
25:21
CPU/Local Master-
Int
These bits are set by the CPU/Local Master by writing
‘0’ to generate an interrupt on the PCI bus. They are
cleared when the PCI writes ‘0’.
0x0
29:26
PCIInt
These bits are set by the PCI by writing ‘0’ to generate
an interrupt on the CPU/Local Master. They are
cleared when the CPU/Local Master writes ‘0’.
0x0
相關(guān)PDF資料
PDF描述
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器)
GT5-2/1S-HU RECTANGULAR CONNECTOR
GT5-1S-HU(A) RECTANGULAR CONNECTOR
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