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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 93/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
9.
Interrupt Controller
The GT-64111 includes an interrupt controller that routes internal interrupt requests to both the CPU/Local Master and
the PCI bus.
The interrupt controller ORs all internal interrupt sources and asserts an interrupt to the CPU/Local Master or to the PCI
when one or more internal interrupts are asserted. There is one Cause register and two Mask registers. The Cause
register has one bit for each interrupt source. If the source asserts an interrupt, its respective bit in the Cause register
will be set. This bit can be read by the CPU/Local Master or from the PCI bus.
The interrupt is acknowledged by the CPU/Local Master or by the PCI bus by resetting its bit in the Cause register (writ-
ing zero to the specific bit and one to all other bits). ONE EXCEPTION for the above is the CPUInt ([25:21] and PCIInt
([29:26])) which are used by the PCI to generate interrupt to the CPU and vice versa. These are SET by writing zero
from the interrupt originating side and CLEARED by writing zero from the interrupt destination side. Each interrupt
CPU/Local Master Mask register bit will mask the interrupt from asserting an interrupt to the CPU/Local Master. A zero
in the PCI Mask register bit will mask the interrupt from asserting an interrupt to the PCI.
IntSum in the Interrupt Cause register is the logical OR of bits[29:1], regardless of the Mask registers’ values. This is in
order to be notified via polling if any interrupt occurred within the GT-64111. Therefore, bit[0] of both the CPU/Local
Master Mask and PCI Mask registers is read-only ‘0’.
CPU/Local Master IntSum in the Interrupt Cause register is the logical OR of bits[29:26,20:1], masked by
bits[29:26,20:1] of the CPU/Local Master Mask register. Therefore, bits[25:21] of the CPU/Local Master Mask register,
being non-relevant to interrupts directed to the CPU/Local Master, are read-only ‘0’. Also bits[31:30], being summaries,
are read-only ‘0’.
PCIIntSum in the Interrupt Cause register is the logical OR of bits[25:1], masked by bits[25:1] of the PCI Mask register.
Therefore, bits[29:26] of the PCI Mask register, being non-relevant to interrupts directed to the PCI, are read-only ‘0’.
Also bits[31:30], being summaries, are read-only ‘0’.
相關(guān)PDF資料 |
PDF描述 |
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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