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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 98/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
1.
OVERVIEW
The GT-64111 provides a single-chip solution for designers building systems around 32-bit bus/64-bit internal MIPS
embedded processors. The architecture of the GT-64111 supports several system implementations for different appli-
cations and cost/performance points. It is possible to design a powerful system with minimal glue logic, or add com-
modity logic (controlled by the GT-64111) for differentiated system architectures that attain higher performance.
The GT-64111 has a three bus architecture:
A 32-bit interface to the CPU bus (SysAD bus)
A 32-bit interface to the memory and device subsystem.
A 32-bit interface to the PCI bus.
The three buses are de-coupled from each other in most accesses, enabling concurrent operation of the CPU bus, PCI
devices, and accesses to memory. For example, the CPU bus can write to the on-chip write buffer, a DMA agent can
move data from DRAM to its own buffers, and a PCI device can write into an on-chip FIFO, all simultaneously.
1.1
CPU bus Interface
The GT-64111 SysAD bus allows the CPU and other local bus masters to access the PCI and memory/device buses.
The SysAD bus protocol supports byte and 32-bit word operations with burst lengths up to 8 words (sub-word, 2 word,
and 4 word transfers are also supported.) With a maximum frequency of 66MHz, the CPU can transfer in excess of 150
Mbytes/sec.
The GT-64111 can automatically determine if the attached MIPS processor is using the 8-bit SysCmd protocol
(RC4640, RM523X) or the 5-bit SysCmd protocol (VR4300).
1.2
DRAM and Device Interface
The GT-64111 has a flexible DRAM controller that supports EDO as well as standard page mode DRAMs. With 45ns
standard DRAMs, the GT-64111 can return data at 8-2-2-2-2-2-2-21 clocks with 32-bit DRAMs and at 8-1-1-1-1-1-1-1
clocks with 64-bit interleaved DRAMs to the CPU bus- at 66Mhz local bus speed. (In “wait-state” nomenclature this
equates to 5-1-1-1-1-1-1-1 and 5-0-0-0-0-0-0-0.) The DRAM controller supports different depth devices in each bank.
NOTE: The performance acheived in interleave mode is equivalent to that possible with SDRAM. Furthermore, EDO
does not have the granularity/memory waste issues associated with SDRAM (i.e. it is easy to build the smaller arrays
required in many systems.)
The GT-64111 memory controller supports different types of memory and I/O devices. It has the control signals and the
timing programmability to support devices such as Flash, EPROMs, SRAMs, FIFOs, and I/O controllers. Device widths
from 8-bits to 64-bits are supported.
Parity generation and checking is supported externally and is optional for each bank of DRAM or any other device on
the memory bus.
1.3
PCI Interface
The GT-64111 interfaces directly with the PCI bus. The GT-64111 can be either a master initiating a PCI bus operation,
or a target responding to a PCI bus operation. The GT-64111 incorporates 96-bytes of posted write and read prefetch
buffers for efficient data transfer between the CPU bus/DMA to PCI, and PCI to main memory.
The GT-64111 becomes a PCI bus master when the CPU bus or the internal DMA engine initiates a bus cycle to a PCI
device. The following PCI bus cycles are supported: Memory Read/Write, Interrupt Acknowledge, Special, I/O Read/
Write, or Configuration Read/Write.
The GT-64111 acts as a target when a PCI device initiates a memory access (or an I/O access in the case of internal
registers). It responds to all memory read/write accesses, as well as to all configuration and I/O cycles in the case of
internal registers.
The GT-64111 contains the required PCI configuration registers. All internal registers, including the PCI configuration
1. Note that Galileo uses “total clock” nomenclature and not “wait-state” nomenclature. This means that 8-1-1-1... means 8 clocks to the
first data, 1 clock for each additional data (zero wait-states).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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