- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67672 > GT-64111 (Galileo Technology Services, LLC) System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 71/130頁 |
| 文件大小： | 881K |
| 代理商： | GT-64111 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
In the case of DRAM or device writes, parity should be generated by external logic (i.e. 511s). In the case of DRAM or
device reads, parity errors should be detected by external logic. If parity error checking is enabled for a particular bank,
and a parity error is detected by the external logic on a CPU read cycle, it will report this error to the GT-64111 via the
ParErr* pin. On CPU read accesses from a 32-bit device or memory, the GT-64111 will not assert SysCmd[4] even if
the bank that was accessed has the parity integrity bit set. If a parity error is detected in this case (indicated by Par-
Err*), the GT-64111 will return the data with SysCmd[5] asserted and will cause a parity error interrupt. In DMA read
accesses, detection of a parity error from a bank with the parity integrity bit set, will cause an interrupt.
In the case of PCI read accesses, the GT-64111 will assert SErr* (if unmasked) if the bank that data was read from has
the parity integrity bit set, and will assert a parity error interrupt. The GT-64111 will generate and check word (32 bits)
parity on data that is read from the PCI with compliance to the PCI requirements for every transaction. A parity error
detection on the PCI will cause the assertion of PErr*.
5.5
Addressing
When the CPU reads a block of data from the memory controller, the controller will read it from DRAM or devices in
sub-block order and the GT-64111 will return the data to the CPU in sub block order. For more information about sub
block ordering, please see your CPU manual.
When a PCI master or the DMA Controller accesses data from the memory controller, data is always addressed lin-
early.
5.6
Memory Interface Restrictions
1.
If latches are not present, all banks must be programmed to be on the even bus. Programming the registers to 64-
bit mode or to dynamically controlled latches will result in an error.
2.
Unless the boot device is 64-bits wide, the boot must be on the even bank.
3.
For 8 and 16-bit devices, all Device Parameters except Turnoff (Section 5.2.2 - Section 5.2.6) must be greater or
equal to 3. i.e., AccToFirst, AccToNext, ADSToWr, WrActive and WrHigh.
4.
For 32 and 64-bit devices, the fastest timing parameters (best performance) are as follows:
AccToFirst = 3
AccToNext = 1 (if latches are transparent) or 2 (if latches are active)
ADSToWr = 2
WrActive = 1
WrHigh = 1
5.
When working with an 8- or 16-bit configured bank from CPU, a read/write operation can not exceed 64-bits (8
bytes).
6.
When working with an 8- or 16-bit configured bank from DMA/PCI, a read/write operation can’t exceed 32-bits (4
bytes).
7.
When an erroneous address is issued or a burst operation is performed to an 8- or 16-bit device, the GT-64111
forces an interrupt (unless masked). If a sequence of address misses occurs, there will be no other interrupt prior
to resetting the appropriate bit in the cause register and no new address will be registered in the Address Decode
Error register (0x470) prior to reading it.
8.
When the CPU reads from an address which is decoded in the CPU Interface Unit as being a hit for CS[2:0]* or
CS[4:3]* and decoded as a miss in the DRAM/Device Interface Unit, the cycle will complete only if Ready* is
asserted (i.e., driven LOW). Although being a result of improper and inconsistent programming of the address
space defining registers, the following 2 workarounds exist:
Ready* should always be asserted (LOW) when CSTiming* is inactive (HIGH).
If the Ready* signal is not needed in the system, the DMAReq[0]/Ready* pin should either be programmed as
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。