參數(shù)資料
型號： GT-64111
廠商： Galileo Technology Services, LLC
英文描述： System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器）
文件頁數(shù)： 91/130頁
文件大?。?/td> 881K
代理商： GT-64111
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
4.
When using the address hold option in the source direction (see Section 7.2.2), the source address should keep
the following rules:
word-aligned if burst limit is greater or equal to 4 bytes.
bits [1:0] equal to 00, 01 or 10 if burst limit is equal to 2 bytes.
no restriction for burst limit equal to 1 byte.
5.
When using the address hold option in the destination direction (see Section 7.2.3), the following rules should be
kept:
both Source and Destination addresses should be word-aligned if burst limit is greater or equal to 4 bytes.
bit [0] of both Source and Destination addresses should be equal to 0 if burst limit is equal to 2 bytes.
no restriction for burst limit equal to 1 byte.
6.
Fly-by transfers are not supported.
7.
Records’ addresses must be a multiple of 16 bytes.
8.
If the destination is a device and if DataTransLimit is smaller or equal 4 bytes, the DMAAck* asserts during the
same cycle as the arbitration cycle. Therefore, DMAReq*, which is typically de-asserted based on the assertion of
DMAAck*, is NOT seen in the DMA arbitration cycle. So although the device does not want to be accessed, a new
transfer may begin.
If DataTransLimit is bigger then 4 bytes then there is no problem. In this case, it is recommended to have a
device that can accepts bursts.
A solution when using one channel only and DataTransLim is less equal to 4 is as follows:
STATE A: The first request should be issued after the channel is enabled and the Device has enough room for
DataTransLim. DMAReq* should be asserted for 1 cycle and then deasserted.
STATE B: While DMAAck* is asserted, if the Device has enough room for data, assert the DMAReq* for 1 cycle
and then deassert the request. Remain in STATE B. If the Device has no room for data then do not assert the
DMAReq*. Go to STATE A.
For 16-bit devices, use 4 byte source aligned addresses for data in DRAM, and Device destination addresses
aligned to 4 bytes + 2 while DataTransLim = 4 bytes.
相關(guān)PDF資料
PDF描述
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器)
GT5-2/1S-HU RECTANGULAR CONNECTOR
GT5-1S-HU(A) RECTANGULAR CONNECTOR
GT5-1S-HU(B) RECTANGULAR CONNECTOR
GT5-2S-HU RECTANGULAR CONNECTOR
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