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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 69/130頁(yè) |
| 文件大小： | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
Figure 21: Extending WrActive Parameter on Write Cycle
5.2.11 Device Bank Width and Location
Bit 21:20 of the Device Bank[3:0] Parameter registers (0x45c-0x46c), DevWidth, specifies whether the data width of
the particular device bank is 8, 16, 32 (default except for BootCS*), or 64-bit (32-bit interleaved). If the bank is set for 8,
16 or 32-bit, it can be placed on the even or odd bank depending on the setting of DevLoc. If the DevWidth is pro-
grammed to ‘11’ indicating the bank is set for 64-bit (32-bit interleaved), the setting of DevLoc is irrelavent as both
banks will be populated. Selecting the even or the odd bank allows for load balancing.
5.2.12 SysAD to AD Addressing
When an address is presented on the SysAD bus which decodes to a peripheral on the device controller, the address
will be conveyed on the AD bus according to Table 18.
TABLE 18. SysAD to AD Addressing
1. AD3 and AD2 are not used when addressing 32 or 64-bit devices.
Device Width
SysAD[24]..
SysAD[5]
SysAD[4]
SysAD[3]
SysAD[2]
SysAD[1]
SysAD[0]
8-bit
AD23..AD4
AD3
AD2
BAdr[2]
BAdr[1]
BAdr[0]
16-bit
AD23..AD4
AD3
AD2
BAdr[2]
BAdr[1]
N/A
32-bit1
AD23..AD4
BAdr[2]
BAdr[1]
BAdr[0]
N/A
64-bit
AD23..AD4
BAdr[2]
BAdr[1]
N/A
ADDRESS
TClk
ALE
ADS* 1
AD[31:0]
ADStoWr = 3
WrActive = 3
WrHigh= 3
WrActive programmed to 3
EWr
OWr 3
GT-64011 DRIVES VALID DATA 1
GT-64011 DRIVES VALID DATA 2
CS* 2
CSTiming*
DevRW*
Notes:
1. Assumes DAdr11/ADS* is programmed to be ADS* only.
2. CS* is driven off the same rising TClk* as ALE (and ADS*). Throughout consecutive transactions to the same device, CS* will remain
asserted. This is why CS* must ALWAYS be qualified with CSTiming*.
3. EWr[3:0]* and OWr[3:0]* are asserted and deasserted from the falling edge of TClk.
4. Ready* is asserted on last rising TClk of WrActive, therefore, the GT-64011 assumes the device is written to correctly and continues to the
next write cycle.
5. Ready* is deasserted on the last rising TClk of WrActive, therefore, the GT-64011 does NOT continue to the next write cycle effectly
extending the WrActive parameter. EWr*/OWr* remains asserted.
6. Ready* is asserted on the next rising TClk, therefore, the GT-64011 assumes the device has been written to correctly and co ntinues to the
next cycle (end of write transaction). Effectively, WrActive is 4 (instead of the programmed 3). For clarification, if there w as another word to
burst, WrHigh would start counting from the rising TClk denoted by 6, not 5.
Ready*
4
5
6
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