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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 84/130頁(yè) |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
7.1
DMA Channel Registers
Each DMA Channel record consists of the following data fields which can be written by the CPU, PCI, or DMA control-
ler in the process of fetching a new record from memory:
Byte count (0x800 - 0x80c). This register is programmed with a 16-bit number which contains the number of
bytes of data that this channel must DMA. The maximum number of bytes which a the DMA channel can be
configured to transfer is 64K. This register will decrement at the end of every burst of transmitted data from
source to destination. When the byte count register is 0, the DMA transaction is finished.
Source address (0x810 - 0x81c). This register is programmed with a 32-bit address. This is the source
address for data and can be from the DRAM, Device or from PCI. This register will either increment, decre-
ment, or hold the same value according to bits 3:2 of the Channel Control Register (see Section 7.2.2).
Destination address (0x820 - 0x82c). This register is programmed with a 32-bit address. This is the destina-
tion address for data and can be to the DRAM/Device or to PCI. This register will either increment, decrement,
or hold the same value according to bits 5:4 of the Channel Control Register (see Section 7.2.3).
Pointer to the next record (0x830 - 0x83c). The register contains a 32-bit address where the values for the
next DMA Channel record can be loaded for chained operation. This can be from the DRAM/Device controller
or from PCI. The byte count, source address, and destination address must be located at sequential
addresses. This register is only used when the channel is configured for Chained Mode (see Section 7.2.5). A
value of ‘0’ (NULL) for this register indicates this is the last record in the chain. See below for more information
about Chained DMA mode.
7.2
DMA Channel Control Register (0x840 - 0x84c)
Each DMA Channel has its own unique Control Register where certain DMA modes can be programmed. Following are
the bit descriptions for each field in the control register.
7.2.1
AddControl[1:0], GT-64111-P-1 ONLY
AddControl[1:0] are for Source and Destination address control for PCI devices (regardless of the CPU Interface unit's
address decoding). In other words, the DMA will access PCI Memory regardless of the results of the address decoding
in the CPU Interface unit if the proper bit is set.
TABLE 22. Setting AddControl[1:0]
7.2.2
SrcDir, bits[3:2]
The SrcDir field contains information about how the source address for the DMA transfer is handled. These bits, if set
to ‘00’ (default), will automatically increment the source address. If set to ‘01’, the source address will automatically
decrement. If set to ‘10’, the source address will remain constant throughout the DMA burst. ‘11’ is a reserved setting
and these bits must not be set to this value.
7.2.3
DestDir, bits[5:4]
The DestDir field contains information about how the destination address for the DMA transfer is handled. These bits, if
set to ‘00’ (default), will automatically increment the destination address. If set to ‘01’, the destination address will auto-
matically decrement. If set to ‘10’, the destination address will remain constant throughout the DMA burst. ‘11’ is a
reserved setting and these bits must not be set to this value.
AddControl[0]
AddControl[1]
Source
Destination
0
CPU Address Space
1
0
PCI Memory Space
CPU Address Space
0
1
CPU Address Space
PCI Memory Space
1
PCI Memory Space
相關(guān)PDF資料 |
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
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| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
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