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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 52/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
28
Revision 1.0
4.2
PCI Side Decoding Process
Decoding on the PCI side starts with the PCI address being compared with the values in the various Base Address
Registers. For example, the RAS[1:0] Base Address Register sets the PCI base address range in which the Ras0* and
Ras1* signals are active (i.e. where DRAM banks 0 and 1 are located in PCI space.)
The size of the “window” in PCI space for each Base Address Register is set by the Bank Size registers for each Base
Address Register. The bank size sets which address bits are significant for the comparison between the active PCI
address and the values in the Base Address Registers (see Figure 8).
Figure 8: Bank Size Register Function Example (16Meg Decode)
The comparison works as follows:
Bits 31:N of the PCI address are compared against bits 31:N in the various Base Address Registers (BAR).
These values much match exactly. The value of ‘N’ is set by the least significant bit with a ‘0’ in the Bank Size
Registers (for example, ‘N’ would be equal to 24 in the example shown in Figure 8, above.)
If all of the above is true, then the resource group is selected and a subdecode is perfomed to determine the
specific resource.
Once a resource group has been decoded by a BAR, it must be subdecoded to determine which physical device
should be accessed within that group. This decoding is controlled by the Device Low and High decode registers.
Note
that these registers are the same ones used for CPU/Local Master-side decoding. This means that the PCI and SysAD
memory maps are coupled at the device decoders. Address bits 27:20 (the bits compared by the Device decoders) for
any given device overlap in both the PCI and SysAD maps.
The sub-decoding comparison works as follows:
Bits 27:20 of the PCI address are then compared against bits the relevant device Low decode registers. The
value of the PCI address bits must be greater than or equal to the Low decode value. This sets the lower
boundary for the sub-decode region.
Bits 27:20 of the PCI address are then compared against the relevantbdevice High decode registers. The
value of the PCI address bits must be less than or equal to this value. This sets the upper bound for the sub-
decode region.
If all of the above are true, then the specific device is selected and an access to that device is performed.
Note that the coupling of the SysAD, PCI, and device memory maps requires special attention for designers of PC Plug
and Play adapters. Please see Galileo’s apnote for this application on our website.
4.3
Disabling the Device Decoders
Any Device sub-decoder can be disabled by setting the value of the “Low” decoder to be higher than the “High”
decoder.
4.4
DMA Unit Address Decoding
The DMA controller uses the address mapping of the CPU/Local Master interface when accessing the device/DRAM
bus. The DMA Unit can access the PCI bus independent of the CPU/Local Master-side PCI bridge decoders on the
GT-64011 and GT-64060 devices only (see DMA section.)
0
1
31
30
29
28
27
26
25
24
23
22
21
20
1
Bank Size Reg
PCI Address
Bits
1
19
18
17
16
15
14
13
12
1
=
x
'=' means must match exactly
'x' means don't care
Comparison
against PCI
address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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