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參數資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數： | 70/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
44
Revision 1.0
5.3
Data Latches
Since both the DRAM and device controller share the AD bus for data transactions, typical system have multiple
devices attached to the AD bus. The GT-64111’s AD bus provides +-16mA of drive and is tested to meet all timing
requirements with a maximum load of 50pF. As typical DRAM configurations require multiple chips and often SIMMs
which greatly load the bus, in addition to other devices, the capacitive load can easily exceed 50pF. Excessive capac-
itive loading will make the rise and fall times of the signals driven by the AD bus become much longer and may cause
timing violations.
The solution to a heavily loaded AD bus is to add latches which act as strong drivers for greater fanout. Using external
latches also improves timing since data does not need to be sampled precisely on a certain clock edge. Instead, the
latched data is valid on the bus longer and the window for clocking in the data is wider. This is extremely important with
Fast Page Mode DRAM since data becomes invalid as soon as CAS* is de-asserted. Without latching the data, the
CAS* assertion time must be extended to meet the GT-64111’s setup and hold requirements. A longer CAS* assertion
time will degrade the overall system performance.
NOTE:
Latches are REQUIRED for 64-bit DRAM or devices.
The GT-64111 outputs all of the control signals for a standard 501 bi-directional latch. There is a separate set of latch
control signals for both the even and odd banks as shown in Table 19.
TABLE 19. Memory Controller Latch Controls for DRAM and Devices
NOTE:
The latch signals are ALWAYS active during DRAM and device writes.
5.3.1
Enabling Latch Control Signals on Read Transactions
Enabling the latch signals on DRAM read cycles is set by bit 18, DRAMLatch, of the DRAM Configuration Register
(0x448). This controls the read latch signals for all DRAM banks. If DRAMLatch is set to 0, the latch control signals are
active on read accesses. If DRAMLatch is set to 1, the external data latches are transparent in DRAM read accesses
when CASRd* is programmed to be one cycle long.
If CASRd* is programmed to be 2 cycles, the latch enables will
always be active regardless of DRAMLatch setting.
Enabling the latch signals on device read cycles is set by bit 25, LatchFunc, of the Device Bank Parameters Registers
(0x45c-0x46c). Each device bank can be individually configured to have latch control signals active during device
reads. If LatchFunct is set to 0, the external data latches are transparent on all device read cycles for this particular
device bank. If LatchFunct is set to 1, the latch control signals are active on read accesses.
5.4
Parity Checking Support
Each bank of DRAM and devices can be configured individually for parity checking. This allows the flexibility to desig-
nate certain banks for peripherals which support parity checking, and other banks for devices which do not. Bit 8 of the
DRAM Bank Parameters Registers (Ox44c to 0x458) controls whether the GT-64111 will sample ParErr* on DRAM
reads. Bit 30 of the Device Parameters Registers (0x45c to 0x46c) controllers whether the GT-64111 will sample Par-
Err* on device reads. ParErr* is sampled on the same rising edge of TClk that data is sampled.
1. The latch enable signals will be active on read cycles only if they are set in the DRAM Bank Parameters Registers or the Device Bank
Parameters Registers. See Section 5.3.1.
Signal
De scr ipt i on
Active Cycles1
A sser te d
fr om TC lk
De - asse rt ed
f r o m Tc lk
LEE, LEO
Latch Enable
DRAM Reads (if config-
ured)
Rising
LEE, LEO
Latch Enable
Device Reads (if config-
ured)
Rising
Falling
LEE, LEO
Latch Enable
DRAM and Device Writes
Rising
Falling
OEE*, OEO*
Output Enable
DRAM and Device Reads
(if configured)
Rising
OEB
Output Enable
DRAM and Device Writes
Rising
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