參數(shù)資料
型號(hào): GT-64111
廠商: Galileo Technology Services, LLC
英文描述: System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
中文描述: 系統(tǒng)控制器(用于RC4640,RM523X和VR4300處理器的系統(tǒng)控制器的RC4640,RM523X和VR4300處理器)
文件頁(yè)數(shù): 99/130頁(yè)
文件大?。?/td> 881K
代理商: GT-64111
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
70
Revision 1.0
11.2
Working With Data Latches
11.2.1 64-bit DRAM
Notes:
1. System supports decrement.
2. System is little endian without decrement.
3. System is big endian without decrement.
4. Signals can be optionally buffered.
5. Be careful if OEB is programmed at reset to have reverse polarity.
6. SysADC[3:0] from the CPU/Local Master too, if parity is supported.
7. Regardless of endianess,
ECAS[0]* and OCAS[0]* always corresponds to SysAD[7:0] and AD[7:0].
ECAS[1]* and OCAS[1]* always corresponds to SysAD[15:8] and AD[15:8].
ECAS[2]* and OCAS[2]* always corresponds to SysAD[23:16] and AD[23:16].
ECAS[3]* and OCAS[3]* always corresponds to SysAD[31:24] and AD[31:24].
Co nnec t io n
Memory
Wi dth
Co nnec t .. .
To ...
DRAM Address1
64-bit
DAdr[11:0]
Even latch outputs
Odd latch outputs
LEAdrE
LEAdrO
Even latch inputs
Odd latch inputs
Even DRAM address pins
Odd DRAM address pins
Even latch LE
Odd latch LE
DRAM Address2
64-bit
DAdr[11:0]4
DAdr[11:0]
Odd latch outputs
LEAdrO
Even DRAM address pins
Odd latch inputs
Odd DRAM address pins
Odd latch LE
DRAM Address3
64-bit
DAdr[11:0]4
DAdr[11:0]
Even latch outputs
LEAdrO
Odd DRAM address pins
Even latch inputs
Even DRAM address pins
Even latch LE
DRAM Data
(Latched)7
64-bit
AD[31:0]
Even latch I/Os B side
‘0’
LEE
OEE*
OEB5
AD[31:0]
Odd latch I/Os B side
‘0’
LEO
OEO*
OEB5
Even latch I/Os A side
Even bank data pins
Even latch CLKAB and CLKBA
Even latch LEAB and LEBA
Even latch OEBA*
Even latch OEAB
Odd latch I/Os A side
Odd bank data pins
Odd latch CLKAB and CLKBA
Odd latch LEAB and LEBA
Odd latch OEBA*
Odd latch OEAB
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