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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 74/130頁 |
| 文件大小： | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
48
Revision 1.0
ter interface or the DMA unit. Upon receiving the first 32-bit word from the PCI target, the data is forwarded to the
requesting unit (CPU/Local Master interface or DMA unit). The GT-64111 supports sub-block ordering during CPU/
Local Master reads, therefore if the original read request address is not aligned to a cache line boundary, the first 32-bit
word returned to the requesting unit will be delayed until it is received from the PCI target, since reads across the PCI
bus are linear.
The GT-64111 internal architecture allows zero wait-state data transfer over the PCI bus (Irdy* continuously asserted)
during both master reads and writes.
6.1.4
PCI Master DMA
The GT-64111’s internal DMA engines can act as PCI bus masters while transferring data to/from the PCI bus. The
DMA engines will only issue memory space read and write cycles. The type of cycle issued follows the same rules as
for the CPU/Local Master. The DMA engines can transfer data between PCI devices using the on-chip DMA FIFOs for
temporary storage.
6.1.5
PCI Master RETRY Counter
RETRY’s detected by the PCI master interface are normally handled transparently from the point of view of the CPU/
Local Master or DMA engines. In some rare circumstances, however, a target device may RETRY the GT-64111
excessively (or forever.) The Retry Counter can be used to recover from this condition. Every time the number of
RETRYs equals the value in the Retry Counter, the GT-64111 will abort the cycle and send an interrupt to the CPU/
Local Master. If the cycle was a read, undefined data is returned and the ERROR bit is set in the data command.
The Retry Counter can be disabled by setting the Retry count to zero.
6.1.6
Cache Line Size
The CacheLine in PCI configuration register at 0x00c specifies the cache line size. The setting of this register specifies
the PCI master policy regarding Memory Read Line/Memory Write & Invalidate commands placed on the PCI bus.
based on the following:
If cache line size is equal to zero, the master will NOT issue Memory Read Line/Memory Write & Invalidate
commands.
For cache line sizes greater than zero but less than or equal seven the master will issue Memory Read Line/
Memory Write & Invalidate commands when the transaction-length matches the cache line size.
For cache line sizes greater than seven, the master will NOT issue Memory Read Line/Memory Write & Invali-
date commands.
6.2
PCI Target Interface
The GT-64111 responses to the following PCI cycles as a target device:
Memory Read
Memory Write
Memory Read Line
Memory Read Multiple
Memory Write and Invalidate
I/O Read
I/O Write
Configuration Read
Configuration Write
The GT-64111 will lock a cache line (32-bytes) in the local memory address space when responding to Lock sequences
on the PCI bus. The GT-64111 will not act as a target for Interrupt Acknowledge, Special, and Dual Address cycles
(these cycles will be ignored.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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