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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 42/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
The last data phase of the write burst is differentiated by from the mid-burst state by the WEOD data identifier driven on
the SysCmd bus. The last data phase of the burst is also entered for the datum written for a single word, or sub-word,
write. On the clock cycle following WEOD, the GT-64111 returns to the idle state.
NOTE:
CPU/Local Master writes cannot be issued as long as WrRdy* is deasserted (HIGH). If WrRdy* is high and an
CPU/Local Master write is attempted, data from previous write cycles may be corrupted (see section 3.4.) Note that all
MIPS compliant processors follow this protocol, it is only DMA engines on the SysAD bus that need to be concerned
with sampling WrRdy* before initiating a write.
3.3
4300 Bus Mode Support (5-bit SysCmd Mode)
The GT-64111 can automatically detect (during the first read transaction) when a 4300 bus compatible processor is
attached. The 4300 uses a 5-bit SysCmd bus encoding that is similar, but incompatible, with the 9-bit SysCmd used by
4640 style processors. All other bus signals and timings are compatible between the two processor bus protocols.
The encodings for SysCmd[4:0] are shown in the tables below. Note that many encodings are not defined; these
encodings are reserved and must not be used. In 4300 mode, SysCmd[8:5] are not used and should be tied to GND. A
summary of bit usage is shown below.
TABLE 5. SysCmd Bit Summary
S ysC md B i t
F unct i o n
SysCmd[4]
0 = Transaction information (read/write/size)
1 = Data information (good/bad/last)
SysCmd[3]
Read/Write Indicator for address cycles
0 = Read transaction
1 = Write transaction
Last data indicator for data cycles
0 = Last data
1 = Not last data
SysCmd[2]
Read/Write Attributesfor address cycles
0 = single read/write
1 = block read/write
Response data indicator for data cycles
0 = response data
1 = not response data
Reserved for CPU driven data cycles
SysCmd[1:0]
Size indicator for reads/writes for address cycles
Error status indicator for data cycles.
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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