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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 77/130頁(yè) |
| 文件大小： | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
50
Revision 1.0
Figure 23: PCI Target Interface FIFOs Operational Example
The target FIFOs are also used for read prefetch. The Memory Read Multiple (MRM) cycle is the only prefetchable
read cycle. In response to any target PCI read cycle, the GT-64111 will read an entire cache line (32 bytes) from mem-
ory into one of the target FIFOs.
If the read is a Memory Read Multiple, as soon as at least two words are delivered from the FIFO to the PCI bus,
another 32 bytes is prefetched into the second FIFO. In this case, the GT-64111 is essentially “guessing” that MRM
cycle will be longer than 32 bytes.
In a non-prefetchable read cycle, data is not fetched into the second FIFO until after all data from the first FIFO is deliv-
ered to the PCI bus.
Cycles to internal registers and Configuration cycles are non-postable or prefetchable.
6.2.2
PCI Target Address Space Decode and Byte Swapping
The GT-64111 decodes accesses on the PCI bus for which it may be a target by the values programmed into its Base
Address Registers (BARs). There are two sets of BARs: regular BARs (in PCI Function 0) and swap BARs (in PCI
Function 1). Accesses decoded by the swap BARs are passed with to/from the target memory device after converting
the endianess of the data (e.g. little-endian to big-endian). Accesses decoded by the regular BARs, by comparison, are
passed without modifying the data to/from the target memory device.
The GT-64111 uses a two stage decode process for accesses through the PCI target interface. Once a PCI accesses
is determined to be a “hit” based on the BAR comparison, the address is passed to the Device Unit for sub-decode. For
example, Base Address Register 0 in Function 0 (BAR0) decodes non-byte swapped accesses to the DRAM controlled
by either RAS0* or RAS1*. The GT-64111 then uses the values programmed into the RAS0 Low and RAS0 High
decode registers to determine if the access is to the DRAM connected to RAS0. Note that the second stage decoders
are shared with the CPU/Local Master (see “CPU/Local Master Address Space Decode” for a nice picture showing
this.)
On reads, if the target PCI address “hits” based on the BAR decode, then misses in the Device Unit, will return random
data. On writes, if the target PCI address “hits” based on the BAR decode, then misses in the Device Unit, the data will
be discarded. In both situations, the MemOut interrupt will be set (bit 1 of the Interrupt Cause Register, 0xc18).
Further, when the GT-64111 is a PCI target and there is a hit in one of the Base Address Registers, the MemEn/IOEn
bit of the Status and Command Register (PCI Config. Register 0x04) must be set to ‘1’ in order for the GT-64111 to
respond to PCI memory/IO transactions. If MemEn/IOEn is set to ‘0’ and there is a hit in one of the Base Address Reg-
12
3
FIFO B (32-BYTES)
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DRAM/DEVICE UNIT
FIFO A (32-BYTES)
PCI BUS
FIFO B (32-BYTES)
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DRAM/DEVICE UNIT
FIFO A (32-BYTES)
PCI BUS
FIFO B (32-BYTES)
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DRAM/DEVICE UNIT
FIFO A (32-BYTES)
PCI BUS
DATA FLOWING INTO FIFO A
FROM PCI. NO DATA FLOWING
INTO DRAM YET. 8 WORDS HAVE
BEEN POSTED FROM PCI.
FIFO A AND B "FLIP". FIFO B IS
NOW TAKING DATA FROM PCI
WHILE FIFO A DRAINS INTO
DRAM. 10 WORDS HAVEN BEEN
POSTED.
PCI BUS HAS COMPLETED
BURST AFTER 10 WORDS. FIFO
A HAS DRAINED AND NOW FIFO
B IS DRAINING INTO DRAM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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