- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67672 > GT-64111 (Galileo Technology Services, LLC) System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) PDF資料下載
參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 45/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
3.4
Operation of WrRdy* and the Internal Write Posting Queues
The GT-64111’s CPU/Local Master interface includes a write posting queue that absorbs local CPU/Local Master
writes at zero wait-states. This is required per the MIPS SysAD bus write protocol.
The write posting queue has 4 address entries and 16 32-bit data entries. The GT-64111 signals if there is “room” in the
CPU/Local Master write posting queue by asserting WrRdy*. If WrRdy* is asserted then the CPU/Local Master may
issue a write of up to 8 words.
WrRdy* will be deasserted the cycle immediately following when:
The address FIFO has two valid entries and a third address is being pushed, or...
The address FIFO has more than two valid entries, or...
The address FIFO has two valid entries or more, the data FIFO has four valid entries and a fifth one is being
pushed, or...
The address FIFO has two valid entries or more, the data FIFO has more than four valid entries, or...
The address FIFO has one valid entry, the data FIFO has six valid entries and a seventh one is being pushed,
or...
The address FIFO has one valid entry, the data FIFO has more than six valid entries.
WrRdy* will be re-asserted the cycle following a transaction away from the states above.
It is not necessary to take the above scenarios into account when designing a system with the GT-64111. MIPS compli-
ant processors such as the R4640 and R4650 sample WrRdy* automatically before issuing a write. Only DMA devices
on SysAD need to be concerned about the functionality of WrRdy*, as mentioned above.
3.5
MIPS Write Modes and Write Patterns Supported
The GT-64111 supports both pipelined and R4000 compatible write modes (with 2 dead cycles between consecutive
writes). The default mode is pipelined, however R4000 mode can be selected in the CPU/Local Master Interface Con-
figuration Register.
The CPU/Local Master interface supports only DDDDDDDD and DXDXDXDXDXDXDXDX write patterns. Be sure to
select one of these two write patterns via the MIPS serial initialization bitstream during the CPU/Local Master reset pro-
cess.
3.6
CPU/Local Master Interface Endianess
The GT-64111 provides the capability to swap the endianess of data transferred to/from the internal registers, to/from
the PCI interface, and to/from the memory bus. Please see the relevant chapter in the applications section for more
information.
1. ‘X’ denotes “don’t care” but ‘X’ signals are driven to a valid 0/1.
TABLE 8. CPU/Local Master Data Identifier SysCmd[4:0] Encodings (driven by CPU/Local
Master
Sy sCm d [4 :0]
En codi ng 1
C o m m and
Mnemo n ic
C o mma nd D esc ri pti o n
4
3
2
1
0
1
0
1
E
X
WEOD
Indicates last valid data in a burst
E = 0 Data is good
E = 1 Data is erroneous
1
E
X
WD
Indicates valid data within a burst
E = 0 Data is good
E = 1 Data is erroneous
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。