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參數(shù)資料
| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 83/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
56
Revision 1.0
7.
DMA Controller
The GT-64111’s DMA Controller consists of four independent channels. The DMA channels are used to optimize sys-
tem performance by moving large amounts of data without CPU intervention. Rather than having the CPU read data
from one source and write it to another, each DMA channels can be programmed to automatically transfer data inde-
pendent of the CPU. This frees the CPU and allows it to continue executing other instructions simultaneous to the
movement of data.
Each DMA channel can move data between DRAM and devices, between devices on the PCI bus, or between DRAM
and devices, and devices on the PCI bus. The four DMA channels request to execute a DMA and if there are simulta-
neous requests, a programmable arbiter which DMA channel will be serviced (see Section 7.5 for more information
about the DMA Arbiter). All DMA transfers use an internal 32-byte FIFO for moving data (see Figure 24). Data is trans-
ferred from the source into the internal FIFO, and from the internal FIFO to the destination. Each DMA channel can be
programmed to move up to 64 KBytes of data per transaction. The burst length of each transfer of DMA can be set
from 1 to 32 bytes. Accesses can be non-aligned both in the source and the destination.
Figure 24: DMA Controller
DMA FIFO
8 x 32 bit
DMA
Arbiter
Byte Count 0
Source Address 0
Destination Address 0
Pointer to Next Record 0
Byte Count 1
Source Address 1
Destination Address 1
Pointer to Next Record 1
Byte Count 2
Source Address 2
Destination Address 2
Pointer to Next Record 2
Byte Count 3
Source Address 3
Destination Address 3
Pointer to Next Record 3
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
Channel 0
Channel 1
Channel 2
Channel 3
DRAM/Device Controller
PCI
DRAM/Device
Source Data
PCI Source Data
DRAM/Device Controller
PCI
PCI Destination
Data
DRAM/Device
Destination Data
Read Data from
Soruce Address
Write Data to
Destination Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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