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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 58/130頁(yè) |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
For example, when using 32-bit DRAM, if bits 5:4 are 01, for a particular bank, an address decoded to that bank from
the SysAD/PAD bus will cause the DAdr bus to act as follows: During RAS* phase, DAdr[9:0] will have the values of
SysAD/PAD[13:5]. During CAS* phase, DAdr[11:0] will have the values of {SysAD/PAD[23:21], SysAD/PAD[16:15],
SysAD/PAD[20:17], SysAD/PAD[4:2]}.
5.1.3
DAdr[11]/ADS* Function
The default state of DAdr[11]/ADS* is to function only as DAdr[11]. Optionally, this pin is software configurable to only
behave as ADS* via bit 17 of the DRAM Configuration register. When this pin functions as ADS*, it is an active LOW
address strobe which indicates the beginning of a device transaction. This pin is sampled as an input at reset for con-
figuration purposes.
5.1.4
Programmable DRAM Timing Parameters
The DRAM controller of the GT-64111 supports a wide range of DRAMs with different access times and each bank can
be programmed independently by the DRAM Bank[3:0] Parameter registers (0x44c-0x458). These paramaters include
the number of clock cycles (based on TClk) that CAS* is asserted (LOW) in a write access (CASWr, bit 0) and in a read
access (CASRd, bit 2). The number of clocks cycles (based on TClk) between active RAS* and CAS* in a write access
(RAStoCASWr, bit 1) and in read access (RAStoCASRd, bit 3) can also be programmed.
5.1.4.1
Asserted CAS*
The number of clocks that CAS* is asserted in LOW in write and read accesses can be programmed to be either one
(Figure 12) or two clocks (Figure 13). 2 clocks is the default number that CAS* is LOW for both write and read
accesses. Both the high and low-going edges of CAS* are driven from a rising TClk.
Figure 12: CAS* Asserted for 1 Clock
Figure 13: CAS* Asserted for 2 Clocks
Selecting the CASWr and CASRd parameter will depend on
DRAM CAS* pulse width minimum requirement time
TClk frequency
For example, standard 60ns EDO DRAM has a 10ns minimum pulse requirement for CAS*. If TClk is set to 50 MHz
(20ns), both CASWr and CASRd can be programmed to one cycle for maximum performance. This will result in read-
ing/writing one datum every two clocks (for 32-bit DRAM). On the other hand, slower Page Mode DRAMs will have
CAS* LOW for 1 TClk
CAS* asserted
from Rising TClk
TClk
. . .
CAS* de-asserted
from Rising TClk
CAS*
CAS* LOW for 2 TClks
CAS* asserted
from Rising TClk
TClk
CAS* de-asserted
from Rising TClk
CAS*
. . .
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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