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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 103/130頁(yè) |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
74
Revision 1.0
12.
Big and Little Endian
12.1
Background
There are two bits in the GT-64111 which control byte swapping. One is located in the CPU/Local Master Interface
Configuration Register (0x000) bit 12. The other is in PCI Internal Command register (0xc00) bit 0. Both bits are given
the same value as sampled at Rst* via pullup/pulldown on Interrupt* pin. Both can be otherwise programmed after
reset is de-asserted. As a master rule, if both bits are set to ‘1’, the GT-64111 assumes Little-endian data format and
NO byte swapping is done within the device. The nomenclature for this section is shown in Table 25.
TABLE 25. Nomenclature
12.1.1 Bit 12 of the CPU/Local Master Interface Configuration register
Bit 12 of the CPU/Local Master Interface Configuration register (0x000) affects the following:
Set to ‘1’ (Little-endian mode): No byte swapping within the CPU/Local Master Interface unit on any data
transfer
Set to ‘0’ (Big-endian mode): Byte swapping of data transfers to/from GT-64111 internal registers (including
Configuration Data register, 0xcfc). No byte swapping of data transfers of which the source/target is external.
12.1.2 Bit 0 of the PCI Internal Command register
Bit 0 of the PCI Internal Command register (0xc00) affects the following:
Set to ‘1’ (No byte swapping): No byte swapping within the PCI Interface unit of any data transfer.
Set to ‘0’ (Byte swapping): No byte swapping of data transfers to/from PCI Interface unit’s internal registers.
Byte swapping of data transfers of which the source/target is external
12.2
Configuring a System for Big and Little Endian
Table 26 shows alll combinations of the resources and swapping bits with sample data.
CPU/Local Master bit = Bit 12 of the CPU/Local Master Interface Configuration register (0x000).
PCI bit = Bit 0 of the PCI Internal Command register (0xc00).
Name
Definition
W, Word
32-bits of data, R4600 terminology.
DW, Double Word
64-bits of data, R4600 terminology.
Even Address
Address of which A[2] == 0.
In Little-endian format this address points to the LEAST significant W of a
DW.
In Big-endian format this address points to the MOST significant W of a DW.
Odd Address
Address of which A[2] == 1.
In Little-endian format this address points to the MOST significant W of a
DW.
In Big-endian format this address points to the LEAST significant W of a DW.
Even Word
LEAST significant W of a DW.
Odd Word
MOST significant W of a DW.
相關(guān)PDF資料 |
PDF描述 |
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
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| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
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| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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