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| 型號(hào)： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁(yè)數(shù)： | 82/130頁(yè) |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
Detect target abort
SERR* will be asserted if SErrEn bit in
Status and Command configuration register is set to 1 and if SERR* is not
masked through
SERR Mask register.
6.7
PCI Bus/Device Bus/CPU/Local Master Clock Synchronization
The PCI interface is designed to run asynchronously with respect to the AD and CPU/Local Master buses. The syn-
chronization delay between these two clock domains can be reduced, however, by running the interfaces in synchro-
nized mode. An example would be having the CPU/Local Master/AD buses running at 66MHz and the PCI bus running
at a 33MHz frequency that was derived from the 66MHz.
Latency through the GT-64111 is reduced to a minimum when synchronized mode is selected. The synchronization
mode is set via the SyncMode bits in the PCI Internal Command register (0xc00).
Note: PClk frequency must be smaller than TClk frequency by at least 1MHz. Please see AC Timing section for more
information.
6.8
66MHz Capability Bit
The 66MHz capability bit in the PCI header is sampled from an external pin at RESET. Note that the state of this bit
does not in any way affect the speed of the PCI interface. It only acts as an “advertisement” to other PCI devices
(or the host CPU) that the GT-64111 is capable of running at 66MHz.
Please see the RESET strapping options section for more details.
6.9
Universal PCI Vio Pin
The Vio pin is used by the GT-64111 to determine the signalling voltage of the PCI interface (3.3V or 5V). This pin is
normally connected to pin 88 on side B of a standard PCI connector when used in a PCI add-in card application.
NOTE: The Vio pin on the GT-64111 was used as the Vref pin on the GT-64011. Vref is used on the GT-64011 to
set the voltage for the CPU interface to be either 3.3V or 5V.
6.10
PCI Interface Restrictions
Note: No PCI access should be attempted before 6 PClk cycles following deassertion of Rst* have expired.
6.10.1 Master
a)
Latency count, as specified in LatTimer (PCI Configuration Register 0x00c), should not be programmed to less
than 6.
6.10.2 Slave
a)
The set bits in the Bank Size registers must be sequential.
b)
When the slave is locked, in order to prevent a deadlock, all transactions to internal registers (I/O or memory
cycles) are not supported (retry will be issued).
c)
Timeout0 (PCI Internal register 0xc04), should not be programmed to less than 2.
6.10.3 Master and Slave
a)
PClk frequency must be smaller than TClk frequency by at least 1MHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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