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參數(shù)資料
| 型號： | GT-64111 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器) |
| 中文描述： | 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器） |
| 文件頁數(shù)： | 73/130頁 |
| 文件大?。?/td> | 881K |
| 代理商： | GT-64111 |
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GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
Revision 1.0
6.
PCI Bus
The GT-64111 includes a Revision 2.1 compliant PCI interface. As a PCI device, the GT-64111 can be either a master
initiating a PCI bus operation or a target responding to a PCI bus operation. Operation up to 66MHz is supported, as is
3.3V and 5V signalling.
6.1
PCI Master Operation
When the CPU/Local Master or the internal DMA machine initiates a bus cycle to a PCI device, the GT-64111 becomes
a PCI bus master and translates the cycle into the appropriate PCI bus cycle. Supported master PCI cycles are:
Memory Read
Memory Write
Memory Read line
Memory Write & Invalidate
I/O Read
I/O Write
Configuration Read
Configuration Write
Interrupt Acknowledge
Special Cycle
Memory Write & Invalidate and Memory Read Line cycles are carried out when the transaction accessing PCI memory
space requests a data transfer equal to the PCI cache line size. When the PCI cache line size is set equal to 0, the GT-
64111 will never issue Memory Write & Invalidate or Memory Read Line cycles.
As a master, the GT-64111 does not issue Dual Address cycles or Lock cycles on the PCI.
The PCI posted write buffer in the GT-64111 permits the CPU/Local Master to complete CPU-to-PCI memory writes
even if the PCI bus is busy. The posted data is written to the PCI device when the PCI bus is available.
6.1.1
PCI Master CPU/Local Master Address Space Decode and Translation
CPU/Local Master access the PCI space through the PCI Memory 0, PCI Memory 1 and PCI I/O decoders in CPU/
Local Master address space. CPU/Local Master accesses that are claimed by these decoders are translated into the
appropriate PCI cycles. The address seen on the CPU/Local Master bus is copied directly to the PCI bus. For example,
if and accesses to 0x1200.0040 is programmed to be bridged as a memory read from PCI, then the active PCI address
for this cycle will be 0x1200.0040. Access to the full PCI space is possible by relocating the CPU/Local Master PCI
decoders within CPU/Local Master space as needed. This relocation can be made transparent to user code by using
the memory remapping capabilities of the CPU/Local Master (MMU or base/bounds function.)
6.1.2
PCI Master CPU/Local Master Byte Swapping
All accesses to PCI space through the CPU/Local Master can have the data byte order swapped as the data moves
through the GT-64111. Byte swapping is turned on via the ByteSwap bit in the PCI Internal Command register (0xc00.)
NOTE: Regardless of the setting of ByteSwap, PCI accesses from a PCI Master to the GT-64111’s internal reg-
isters or PCI Configuration registers will NOT be swapped.
6.1.3
PCI Master FIFOs
The PCI master interface includes a FIFO of 8 entries, each 32 bit. During writes to the PCI interface, it receives write
data from the CPU/Local Master interface or the DMA unit. When the PCI bus is granted, the FIFO delivers the write
data to the target on the PCI bus.
Upon receiving the first 32-bit word from the CPU/Local Master interface or DMA unit, the PCI master interface will
request the PCI bus (if the GT-64111 is not already parked). Once granted, the appropriate write cycle is started on the
PCI bus.
During reads, the PCI master interface FIFO receives read data from the PCI bus and delivers it to the CPU/Local Mas-
相關(guān)PDF資料 |
PDF描述 |
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| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器) |
| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
| GT5-1S-HU(A) | RECTANGULAR CONNECTOR |
| GT5-1S-HU(B) | RECTANGULAR CONNECTOR |
| GT5-2S-HU | RECTANGULAR CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
| GT-64120A-B-0 | 制造商:GALILEO 功能描述: |
| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
| GT64120AB2-BBB1C000 | 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays |
| GT64120AB2-BBB1C083 | 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083 |
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