參數(shù)資料
型號： GT-64111
廠商： Galileo Technology Services, LLC
英文描述： System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器）
文件頁數(shù)： 90/130頁
文件大?。?/td> 881K
代理商： GT-64111
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
62
Revision 1.0
7.8.2
DMA in Block Mode
In block mode no hand shake signals are used to initiate DMA transfers. The DMA unit will complete the transfer once
the CPU has programmed the DMA and enabled it.
7.8.3
Non-Chain Mode
In non-chain mode the CPU or PCI master initiates the DMA channel parameters (Source, Destination Byte Count and
command Registers).The DMA will start to transfer data after the enable bit in the Command register is set to 1. The
DMA remains in an active state until the Byte Count reaches a terminal count or until the channel is disabled.
7.8.4
Chain Mode
In chain mode the DMA channel parameters (Source, Destination Byte Count and Pointer to Next Record) are read
from records located in Memory, Device or PCI. The DMA channel stays in the active state until Pointer to Next Record
is NULL and the Byte Count reaches the terminal count. In this mode, an interrupt can be asserted every time the byte
count reaches the terminal count or when BOTH the Byte Count reaches the terminal count and the Pointer to Next
Record is NULL.
7.8.5
Dynamic DMA chaining
Dynamic chaining is when DMA records are added to a chain which a DMA channel is actively working on. The main
issue is to synchronize between when the GT-64111 reads the last chain record (the NULL pointer) to the time the CPU
changes the current last DMA record. Following is an algorithm which provides this synchronization mechanism.
1.
Prepare the new record.
2.
Change the last record's Pointer to Next Record to point to the new record.
3.
Read the DMA control register.
If the DMAActSt bit is 0 (NOT active) {
Update the Pointer to Next Record in the GT-64111 and assert the FetNexRec bit
}
else
{
read the Pointer to Next Record GT-64111. If it's equal to NULL {
Mark (by using a flag or something) that in the next DMA chain complete interrupt you'll need to -
[[[[{
Update the NRP register in the GT-64010 and Write the Fetch Next Record }]]]]
}
7.9
DMA Restrictions
1.
Transfers of less than 4 bytes are not supported.
2.
When Source or Destination address is decremented, both addresses should be word-aligned (that is, A1 and A0
should be both zero), and Byte Count should be a multiple of 4 (this applies for burst limits greater than 4 bytes).
3.
When the burst limit is less than 4 bytes, no decrement mode (source or destination) is not supported.
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