參數(shù)資料
型號： GT-64111
廠商： Galileo Technology Services, LLC
英文描述： System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
中文描述： 系統(tǒng)控制器（用于RC4640，RM523X和VR4300處理器的系統(tǒng)控制器的RC4640，RM523X和VR4300處理器）
文件頁數(shù)： 57/130頁
文件大?。?/td> 881K
代理商： GT-64111
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs
32
Revision 1.0
(default), RAS[3:0] will not simulataneously assert LOW following the low-going CAS*. Rather, RAS[0] will first go LOW,
followed by RAS[1] on the next TClk, and so on. After the last RAS, RAS[3] has asserted LOW, CAS* will go HIGH
again followed by RAS[0] on the next TClk, RAS[1] on the following TClk, and so on. Staggered Refresh is useful for
load balancing, shown in Figure 11.
Figure 10: Non-Staggered Refresh Waveform
Figure 11: Staggered Refresh Waveform
5.1.2
Assymetrically RAS*/CAS* Addressing
The GT-64111 supports assymetrical RAS*/CAS* addressing. In other words, a different number of addressing bits
may be valid for row addressing as compared to column addressing. 9, 10, 11 or 12 bits can be used for DRAM row
addressing and is specified on a per bank basis by programming bits 5:4 of the DRAM Bank[3:0] Parameter registers
(0x44c-0x458). These bits determine the decoding of an address asserted on the SysAD bus from a device such as a
CPU or from a PCI System on the PCI bus. Some bits of the address are used for RAS* while others are used for
CAS*. The active SysAD or PAD pins which are translated to the DAdr pins are shown in Table 14 for 32-bit DRAM and
in Table 15 for 64-bit DRAM (32-bit interleaved).
TABLE 14. Active DAdr[11:0] bits for RAS* and CAS*, 32-bit DRAM
TABLE 15. Active DAdr[11:0] bits for RAS* and CAS*, 64-bit DRAM (32-bit interleaved)
1. Regardless of 5:4, DAdr[11:0] will always have the value of SysAD/PAD[16:5] during RAS*.
DRAM Bank
Para. 5:4
Row Addr.
Depth
Active RAS*
DAdr Bits1
SysAD/PAD Bits Used
for RAS* on DAdr
SysAD/PAD Bits Used for CAS* on
DAdr[11:0]
00
512
8:0
13:5
22..20, 16..14, 19..17, 4..2
01
1K
9:0
14:5
23..21, 16..15, 20..17, 4..2
10
2K
10:0
15:5
24..22, 16, 21..17, 4..2
11
4K
11:0
16:5
25..17, 4..2
DRAM Bank
Para. 5:4
Row Addr.
Depth
Active RAS*
DAdr Bits1
SysAD/PAD Bits Used
for RAS* on DAdr
SysAD/PAD Bits Used for CAS* on
DAdr[11:0]
00
512
8:0
13:5
23..20, 16..14, 19..17, 4..3
01
1K
9:0
14:5
24..21, 16..15, 20..17, 4..3
10
2K
10:0
15:5
25..22, 16, 21..17, 4..3
11
4K
11:0
16:5
26..17, 4..3
TClk
RAS[3:0]
ECAS[3:0]
OCAS[3:0]
0
F
0
F
TClk
RAS[3:0]
ECAS[3:0]
OCAS[3:0]
8
C
E
F
7
3
1
0F
F
0
相關(guān)PDF資料
PDF描述
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