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Functional Description
5-50
82801AA and 82801AB Datasheet
5.12.4
Dynamic System Clock Control
The ICH has extensive control for dynamically starting and stopping system clocks. The clock
control is used for transitions among the various S0/Cx states, and processor throttling. Each
dynamic clock control method is described in this section. The various Sleep states may also
perform types of non-dynamic clock control.
The ICH supports the ACPI C0, C1, C2 states. The Dynamic Clock control is handled using the
STPCLK# to halt processor instruction stream. A C2 state ends due to a Break event. Based on the
break event, the ICH returns the system to C0 state.
Table 5-36
lists the possible break events.
5.12.4.1
Entering/Exiting the C1 State
Causes of C1 Entry:
From C0 State:
Processor performs an Autohalt instruction.
From C2 State:
STPCLK# goes inactive and the processor had done an Autohalt instruction
prior to STPCLK# going active, and no break event has occurred. The C1 state persists until an
interrupt (regular interrupt, NMI, SMI#, or INIT#) occurs. This C1 state persists only for a few
clocks, since the cause of STPCLK# going inactive is some type of interrupt.
Causes of Exit from C1
To C0 state:
When an enabled interrupt (regular interrupt, NMI, SMI#, or INIT#) occurs.
To C2 state:
STPCLK# goes active. This causes a transition to the C2 state. This case can only
occur if the processor reads the Level 2 register (forcing a transition to C2 state) and the
processor does an autohalt instruction before it recognizes STPCLK# active.
Table 5-36. Break Events
Event
Comment
Any unmasked interrupt goes active
IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC.
Since SCI is an interrupt, any SCI is also a break event.
Any internal event that causes an NMI or SMI#
Many possible sources
Any internal event that causes INIT# to go active
Could be indicated by the keyboard controller via the
RCIN input signal.