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AC’97 Audio Controller Registers (D31:F5)
12-10
82801AA and 82801AB Datasheet
12.2.1
x_BDBAR—Buffer Descriptor Base Address Register
I/O Address:
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
00000000h
No
R/W
Default Value:
Lockable:
Size:
Power Well:
32 bits
Core
12.2.2
x_CIV—Current Index Value Register
I/O Address:
NABMBAR + 04h (PICIV),
NABMBAR + 14h (POCIV),
NABMBAR + 24h (MCCIV)
00h
No
Attribute:
RO
Default Value:
Lockable:
Size:
Power Well:
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32 bit read from address offset 04h. Software can also read this register individually by doing a
single 8 bit read to offset 04h.
12.2.3
x_LVI—Last Valid Index Register
I/O Address:
NABMBAR + 05h (PILVI),
NABMBAR + 15h (POLVI),
NABMBAR + 25h (MCLVI)
00h
No
Attribute:
R/W
Default Value:
Lockable:
Size:
Power Well:
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32-bit read from address offset 04h. Software can also read this register individually by doing a
single 8-bit read to offset 05h.
Bit
Description
31:3
Buffer Descriptor Base address[31:3].
These bits represent address bits 31:3. The data should
be aligned on 8-byte boundaries. Each buffer descriptor is 8 bytes long and the list can contain a
maximum of 32 entries.
2:0
Hardwired to 0.
Bit
Description
7:5
Hardwired to 0
4:0
Current Index Value[4:0]
. These bits represent which buffer descriptor within the list of 32
descriptors is currently being processed. As each descriptor is processed, this value is
incriminated. The value rolls over after it reaches 31.
Bit
Description
7:5
Hardwired to 0.
4:0
Last Valid Index[4:0].
This value represents the last valid descriptor in the list. This value is
updated by the software each time it prepares a new buffer and adds it to the list.