
LPC Interface Bridge Registers (D31:F0)
8-24
82801AA and 82801AB Datasheet
8.2.4
DMACMD—DMA Command Register
I/O Address:
Ch. #0
–
3 = 08h;
Ch. #4
–
7 = D0h
Undefined
No
Attribute:
Size:
Power Well:
WO
8 bits
Core
Default Value:
Lockable:
8.2.5
DMASTA—DMA Status Register
I/O Address:
Ch. #0
–
3 = 08h;
Ch. #4
–
7 = D0h
Undefined
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Default Value:
Lockable:
Bit
Description
7:5
Reserved. Must be 0.
4
DMA Group Arbitration Priority.
Each channel group is individually assigned either fixed or rotating
arbitration priority. At part reset, each group is initialized in fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
3
Reserved. Must be 0
2
DMA Channel Group Enable.
Both channel groups are enabled following part reset.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded
through channel 4.
0 = Enable the DMA channel group.
1:0
Reserved. Must be 0.
Bit
Description
7:4
Channel Request Status.
When a valid DMA request is pending for a channel, the corresponding bit
is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set to
0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the
cascade channel, so the request status of channel 4 is a logical OR of the request status for channels
0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
3:0
Channel Terminal Count Status.
When a channel reaches terminal count (TC), its status bit is set to
1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the
TC bit response for channel 4 is irrelevant:
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)