
82801AA and 82801AB Datasheet
8-61
LPC Interface Bridge Registers (D31:F0)
8.8.3.5
PROC_CNT—Processor Control Register
I/O Address:
PMBASE + 10h
(
ACPI P_BLK)
00000000h
No (bits 8:6 are write once)
Core
Attribute:
Size:
Usage:
R/W
32 bits
ACPI or Legacy
Default Value:
Lockable:
Power Well:
Bit
Description
31:18
Reserved.
17
THTL_STS—RO.
This bit indicates if the clock state machine is in a low power state.
1 = Indicates that the clock state machine is in some type of low power state (where the processor is
not running at its maximum performance): thermal throttling or hardware throttling.
7:5
THRM_DTY.
This write-once 3-bit field determines the duty cycle of the throttling when the thermal
override condition occurs. The duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle period is 1024
PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the C2 state, no
throttling occurs.
There is no enable bit for thermal throttling, because it should not be disabled. Once the
THRM_DTY field is written, any subsequent writes will have no effect until PCIRST# goes active.
THRM_DTY
Throttle Mode
PCI Clocks
000
RESERVED (Default)
512
(Will be 50%)
001
87.5%
896
010
75.0%
768
011
62.5%
640
100
50%
512
101
37.5%
384
110
25%
256
111
12.5%
128
4
THTT_EN.
When set and the system is in a C0 state, it enables a processor-controlled STPCLK#
throttling. The duty cycle is selected in the THTL_DTY field.
1 = Enable
0 = Disable
3:1
THTL_DTY.
This 3-bit field determines the duty cycle of the throttling when the THTL_EN bit is set.
The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted (low)
while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs.
THTL_DTY Throttle Mode
PCI Clocks
000
RESERVED (Default)
512
(Will be 50%)
001
87.5%
896
010
75.0%
768
011
62.5%
640
100
50%
512
101
37.5%
384
110
25%
256
111
12.5%
128
0
Reserved