
82801AA and 82801AB Datasheet
13-3
AC ’97 Modem Controller Registers (D31:F6)
13.1.4
PCISTA—Device Status Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
07h
–
06h
0280h
No
Attribute:
Size:
Power Well:
R/WC
16 bits
Core
PCISTA is a 16-bit status register. Refer to the
PCI 2.1 specification
for complete details on each
bit.
13.1.5
RID—Revision Identification Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
08h
See ICH Spec. Updates
No
Attribute:
Size:
Power Well:
RO
8 Bits
Core
13.1.6
PI—Programming Interface Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
09h
00h
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
Description
15
DPE (Detected Parity Error)—RO. Not implemented. Hardwired to "0".
14
SERRS (SERR# Status) —RO. Not implemented. Hardwired to "0".
13
MAS (Master-Abort Status)
—R/WC.
1 = Bus Master AC ‘97 interface function, as a master, generates a master abort.
0 = Software clears this bit by writing a "1" to this bit.
12
Reserved. Read as “0”.
11
STA (Signaled Target-Abort Status) —RO. Not implemented. Hardwired to "0".
10:9
DEVT (DEVSEL# Timing Status)—RO
.
This 2-bit field reflects the ICH's DEVSEL# timing parameter.
These read only bits indicate the ICH's DEVSEL# timing when performing a positive decode.
8
DPD (Data Parity Detected) —RO. Not implemented. Hardwired to "0".
7
FBC (Fast Back to back Capable) —RO. Hardwired to "1". This bit indicates that the ICH as a target
is capable of fast back-to-back transactions.
6
UDF Supported—RO. Not implemented. Hardwired to "0".
5
66 MHz Capable—RO. Hardwired to "0".
4:0
Reserved. Read as 0's.
Bit
Description
7:0
Revision ID Value.
8-bit value that indicates the revision number for the AC’97 Modem
Controller. Refer to the ICH Specification Updates for this value.
Bit
Description
7:0
Programming Interface Value.