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Register Index
A-8
82801AA and 82801AB Datasheet
Table A-2. ICH Fixed I/O Registers (Sheet 1 of 4)
Register Name
Port
Datasheet Section and Location
Channel 0 DMA Base & Current
Address Register
Channel 0 DMA Base & Current
Count Register
Channel 1 DMA Base & Current
Address Register
Channel 1 DMA Base & Current
Count Register
Channel 2 DMA Base & Current
Address Register
Channel 2 DMA Base & Current
Count Register
Channel 3 DMA Base & Current
Address Register
Channel 3 DMA Base & Current
Count Register
00h
Section 8.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 8-22
Section 8.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 8-23
Section 8.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 8-22
Section 8.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 8-23
Section 8.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 8-22
Section 8.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 8-23
Section 8.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 8-22
Section 8.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 8-23
Section 8.2.4, “DMACMD—DMA Command Register”
on page 8-24
Section 8.2.5, “DMASTA—DMA Status Register” on
page 8-24
Section 8.2.6, “DMA_WRSMSK—DMA Write Single
Mask Register” on page 8-25
Section 8.2.7, “DMACH_MODE—DMA Channel Mode
Register” on page 8-25
Section 8.2.8, “DMA Clear Byte Pointer Register” on
page 8-26
Section 8.2.9, “DMA Master Clear Register” on
page 8-26
Section 8.2.10, “DMA_CLMSK—DMA Clear Mask
Register” on page 8-26
Section 8.2.11, “DMA_WRMSK—DMA Write All Mask
Register” on page 8-27
01h
02h
03h
04h
05h
06h
07h
Channel 0-3 DMA Command
Register
Channel 0-3 DMA Status Register
08h
Channel 0-3 DMA Write Single
Mask Register
Channel 0-3 DMA Channel Mode
Register
Channel 0-3 DMA Clear Byte
Pointer Register
Channel 0-3 DMA Master Clear
Register
Channel 0-3 DMA Clear Mask
Register
Channel 0-3 DMA Write All Mask
Register
Aliased at 00h
–
0Fh
Master PIC ICW1 Init. Cmd Word 1
Register
Master PIC OCW2 Op Ctrl Word 2
Register
Master PIC OCW3 Op Ctrl Word 3
Register
Master PIC ICW2 Init. Cmd Word 2
Register
Master PIC ICW3 Init. Cmd Word 3
Register
Master PIC ICW4 Init. Cmd Word 4
Register
Master PIC OCW1 Op Ctrl Word 1
Register
Aliased at 20h
–
21h
Aliased at 20h
–
21h
Aliased at 20h
–
21h
Aliased at 20h
–
21h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h–1Fh
20h
Section 8.4.2, “ICW1—Initialization Command Word 1
Register” on page 8-33
Section 8.4.8, “OCW2—Operational Control Word 2
Register” on page 8-36
Section 8.4.9, “OCW3—Operational Control Word 3
Register” on page 8-37
Section 8.4.3, “ICW2—Initialization Command Word 2
Register” on page 8-34
Section 8.4.4, “ICW3—Master Controller Initialization
Command Word 3 Register” on page 8-34
Section 8.4.6, “ICW4—Initialization Command Word 4
Register” on page 8-35
Section 8.4.7, “OCW1—Operational Control Word 1
(Interrupt Mask) Register” on page 8-35
21h
24h–25h
28h–29h
24h–25h
2Ch–2Dh