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Functional Description
5-44
82801AA and 82801AB Datasheet
FERR#/IGNNE# (Coprocessor Error)
The ICH supports the coprocessor error function with the FERR#/IGNNE# pins. The function is
enabled via the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, bit 13). FERR# is tied
directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the
processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register,
the ICH negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until
FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.
If COPROC_ERR_EN is not set, then the assertion of FERR# will have not generate an internal
IRQ13, nor will the write to F0h generate IGNNE#.
NMI
Non-Maskable Interrupts (NMIs) can be generated by several sources.
Table 5-27. INIT# Going Active
Cause of INIT# Going Active
Comment
Shutdown special cycle from processor.
PORT92 write, where INIT_NOW (bit 0) transitions from a 0 to a 1.
PORTCF9 write, where RST_CPU (bit 2) was a 0 and SYS_RST(bit 1)
transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected to be driven by the
external microcontroller (KBC).
0 to 1 transition on RCIN# must
occur before the ICH arms
INIT# to be generated again.
Processor BIST (ICH: 82801AA only)
To enter BIST, the software
sets CPU_BIST_EN bit and
then does a full processor reset
using the CF9 register.
Figure 5-10. Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
Table 5-28. NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally, externally
via SERR# signal, or via message from the host
controller)
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).