
LPC Interface Bridge Registers (D31:F0)
8-70
82801AA and 82801AB Datasheet
8.9
System Management TCO Registers (D31:F0)
The TCO logic is accessed via registers mapped to the PCI configuration space (Device
31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC Device
31:Function 0 PCI Configuration registers.
8.9.1
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is,
ACPIBASE + 60h in the PCI config space.
Table 8-11
shows the mapping of the registers within
that 32-byte range. Each register is described in the following sections.
NOTE:
1. Reserved registers are read only and are not shown.
8.9.2
TCO1_RLD—TCO Timer Reload and Current Value
I/O Address:
Default Value:
Lockable:
TCOBASE +00h
0000h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
8.9.3
TCO1_TMR—TCO Timer Initial Value
I/O Address:
Default Value:
Lockable:
TCOBASE +01h
0004h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Table 8-11. TCO I/O Register Map
Offset
Read/Write
Register Name
00h
R/W
TCO_RLD: TCO Timer Reload and Current Value
01h
R/W
TCO_TMR: TCO Timer Initial Value
02h
R/W
TCO_DAT_IN: TCO Data In
03h
R/W
TCO_DAT_OUT: TCO Data Out
04h
–
05h
R/W
TCO1_STS : TCO Status
06h
–
07h
R/W
TCO2_STS : TCO Status
08h
–
09h
R/W
TCO1_CNT: TCO Control
0Ah
–
0Bh
R/W
TCO2_CNT: TCO Control
Bit
Description
7:0
Reading this register returns the current count of the TCO timer. Writing any value to this register
reloads the timer to prevent the timeout. Bits 7:6 are always be 0.
Bit
Description
7:6
Reserved
5:0
Value that is loaded into the timer each time the TCO_RLD register is written. Values of 0h
–
3h are
ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and this
allows timeouts ranging from 2.4 seconds to 38 seconds.