
82801AA and 82801AB Datasheet
8-7
LPC Interface Bridge Registers (D31:F0)
8.1.12
BIOS_CNTL (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
4E
–
4Fh
0000h
No
Attribute:
Size:
Power Well:
R/W
16 bits
Core
8.1.13
TCO_CNTL — TCO Control (LPC I/F — D31:F0)
Offset Address:
Default Value:
Lockable:
54h
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Bit
Description
15:2
Reserved.
1
BIOS Lock Enable (BLE).
Once set, this bit can only be cleared by a PCIRST#.
1 = Setting the BIOSWE bit will cause SMIs.
0 = Setting the BIOSWE will not cause SMIs.
0
BIOS Write Enable (BIOSWE).
When this bit is written from a ‘0’ to a ‘1’ and BIOS lock Enable
(BLE) is also set, an SMI# is generated. This ensures that only SMM code can update BIOS.
1 = Access to the BIOS space is enabled for both read and write cycles.
0 = Only read cycles result in LPC I/F cycles.
Bit
Description
7:4
Reserved.
3
TCO Interrupt Enable (TCO_INT_EN).
This bit enables/disables the TCO interrupt.
1 = Enables TCO Interrupt, as selected by the TCO_INT_SEL field.
0 = Disables TCO interrupt.
2:0
TCO Interrupt Select (TCO_INT_SEL).
Specifies on which IRQ the TCO will internally appear. If
not using the APIC, the TCO interrupt must be routed to IRQ[9:11], and that interrupt is not
sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the
TCO interrupt can also be mapped to IRQ[20:23], and can be shared with other interrupt. Note that
if the TCOSCI_EN bit is set (bit 6 in this register), then the TCO interrupt will be sent to the same
interrupt as the SCI, and the TCO_INT_SEL bits will have no meaning.
Bits
SCI Map
000
IRQ9
001
IRQ10
010
IRQ11
011
Reserved
100
IRQ20 (Only available if APIC enabled)
101
IRQ21 (Only available if APIC enabled)
110
IRQ22 (Only available if APIC enabled)
111
IRQ23 (Only available if APIC enabled)