![](http://datasheet.mmic.net.cn/330000/INTEL82801_datasheet_16416407/INTEL82801_263.png)
82801AA and 82801AB Datasheet
8-73
LPC Interface Bridge Registers (D31:F0)
8.9.8
TCO1_CNT—TCO1 Control Register
I/O Address:
Default Value:
Lockable:
TCOBASE +08h
0000h
No
Attribute:
Size:
Power Well:
R/W
16 bits
Core
8.9.9
TCO2_CNT—TCO2 Control Register
I/O Address:
Default Value:
Lockable:
TCOBASE +0Ah
0000h
No
Attribute:
Size:
Power Well:
R/W
16 bits
Resume
Bit
Description
15:12
Reserved
11
TCO Timer Halt.
1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI#
or set the SECOND_TO_STS bit.
For the ICH (82801AA), when set, this bit will prevent rebooting and prevent Alert On LAN event
messages (but not Alert On LAN heartbeat messages).
0 = The TCO Timer is enabled to count.
10
ICH (82801AA):
SENDNOW.
1 = Writing a 1 to this bit will cause the ICH to send an Alert On LAN Event message with the
Softwware Event bit set.
0 = The ICH will clear this bit to 0 when it has completed sending the message. Software must not
set this bit to 1 again until the ICH has set it back to 0.
ICH0 (82801AB):
Reserved.
9
NMI2SMI_EN.
Setting this bit to 1 while both NMI_EN bit and SMI_EN bit are set will force all NMI’s
to instead cause an SMI#. This is reported in the TCO1_STS register. The SMI# handler can cause
an NMI by writing a 1 to the NMI_NOW bit.
When this bit is set to 1, no NMI will be generated. If this bit is set to 1, but the NMI_EN bit is not set,
then no NMI or SMI# based on NMI events will be generated.
8
NMI_NOW.
Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an
entry to the NMI handler. The NMI handler is expected to clear this bit. Another NMI is not
generated until the bit is cleared by writing back a 1.
7:0
Reserved
Bit
Description
15:3
Reserved.
2:1
INTRD_SEL.
Selects the action to take if the INTRUDER# signal goes active.
00 = Reserved
01 = Interrupt (as selected by TCO_INT_SEL).
10 = SMI
11 = Reserved
0
Reserved.