![](http://datasheet.mmic.net.cn/330000/INTEL82801_datasheet_16416407/INTEL82801_68.png)
Functional Description
5-18
82801AA and 82801AB Datasheet
5.5.4
Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last
byte of transfer, based upon the size of the transfer.
For example, on an 8 bit transfer size (SIZE field is ‘00b’), if the TC bit is set, then this is the last
byte. On a 16 bit transfer (SIZE field is ‘01b’), if the TC bit is set, then the second byte is the last
byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is
communicated, and only signal TC when the last byte of that transfer size has been transferred.
5.5.5
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a
DMA write, where the peripheral is transferring data to main memory. The indication from the host
is the same as a DMA write, so the peripheral will be driving data onto the LPC interface.
However, the host does not transfer this data into main memory.
5.5.6
DMA Request Deassertion
An end of transfer is communicated to the ICH through a special SYNC field transmitted by the
peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting
LDREQ#. If a DMA transfer is several bytes, such as a transfer from a demand mode device, the
ICH needs to know when to deassert the DMA request based on the data currently being
transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to
the ICH whether this is the last byte of transfer or if more bytes are requested. To indicate the last
byte of transfer, the peripheral uses a SYNC value of ‘0000b’ (ready with no error), or ‘1010b’
(ready with error). These encodings tell the ICH that this is the last piece of data transferred on a
DMA read (ICH to peripheral), or the byte which follows is the last piece of data transferred on a
DMA write (peripheral to ICH).
When the ICH sees one of these two encodings, it ends the DMA transfer after this byte and
deasserts the DMA request to the 8237. Therefore, if the ICH indicated a 16 bit transfer, the
peripheral can end the transfer after one byte by indicating a SYNC value of ‘0000b’ or ‘1010b’.
The ICH does not attempt to transfer the second byte, and deasserts the DMA request internally.
If the peripheral indicates a ‘0000b’ or ‘1010b’ SYNC pattern on the last byte of the indicated size,
then the ICH only deasserts the DMA request to the 8237 since it does not need to end the transfer.
If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of ‘1001b’
(ready plus more data). This tells the 8237 that more data bytes are requested after the current byte
has been transferred, so the ICH keeps the DMA request active to the 8237. Therefore, on an 8 bit
transfer size, if the peripheral indicates a SYNC value of ‘1001b’ to the ICH, the data is transferred
and the DMA request remains active to the 8237. At a later time, the ICH then comes back with
another START - CYCTYPE - CHANNEL - SIZE etc. combination to initiate another transfer to
the peripheral.
The peripheral must not assume that the next START indication from the ICH is another grant to
the peripheral if it had indicated a SYNC value of ‘1001b’. On a single mode DMA device, the
8237 re-arbitrates after every transfer. Only demand mode DMA devices can be guaranteed that
they receive the next START indication from the ICH.